Please take back up of your project first.
Could you please delete the component of DCFIFO , create a new instance of it & try to build it again.
It might help to resolve the issue, if you face any concern let me know.
(This message was posted on behalf of Intel Corporation)
Add the following to the vsim command ..
For Verilog designs:
-L altera_mf_ver -L altera_lnsim_ver -L 220model_ver -L altera_ver
For VHDL designs:
-L altera_mf -L altera_lnsim -L 220model -L altera