In the project I have added the *.sip and the *.qip in the files setting, but only appear the *.qip, seems the simulation *.sip is not correctly define in my project. During the simulation I get errors like Memory is not bounded.
Do you have a test-bench or are you using the msim.tcl for simulation?
If you have test-bench instantiate your design and map the ports to your test bench and make it top level?
If possible share your project.