My design work well on quartus 17.1, after updating to quartus 19.4 the compilation fail on the plan step and i got this error on hps_uart_rx pin F20:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (78, 198) to (78, 199), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): hps_uart0_RX
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad hps_uart0_RX is constrained to the location PIN_F20 due to: User Location Constraints (PIN_F20)
Info (14709): The constrained I/O pad is contained within this pin
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): F20
How to fix this error?
The device is arria 10 10AS066H2F34I2SG and i have a pin assignment in the Pin Planner to pin F20.
This project pass compilation in quartus 17.1.
Since there are lot of difference between 17.1 version of Quartus and 19.4 version , can you check with an intermediate version like 18.1 to see that the issue still exists.
Thanks and Regards