i wanna to convert this code in vhdl

[Altera_Forum]

void main() { SerialPortInit(); /* Serial Communication – 9600-N-8-1 */  

Send2Gsm("AT\r\n"); /* Transmit AT to the module – GSM Modem sends OK */ DelayS(2); /* 2 sec delay */  Send2Gsm("ATE0\r\n"); /* Echo Off */ DelayS(2); /* 2 sec delay */  Send2Gsm("AT+CMGF=1\r\n"); /* Switch to text mode */ DelayS(2); /* 2 sec delay */  Send2Gsm("AT+CMGS=\"+919447367176\"\r\n"); /* Send SMS to a cell number */ DelayS(2); /* 2 sec delay */  Send2Gsm("TEST DATA FROM RhydoLABZ-COCHIN"); /* Input SMS Data */ SerialTx(0x1a); /* Ctrl-Z indicates end of SMS */ DelayS(2); /* 2 sec delay */  while(1);  }

[Altera_Forum]

process main begin SerialPortInit; -- Serial Communication – 9600-N-8-1 Send2Gsm("AT\r\n"); wait for 2 sec; -- Transmit AT to the module – GSM Modem sends OK */ DelayS(2); /* 2 sec delay */ Send2Gsm("ATE0\r\n"); wait for 2 sec; -- Echo Off */ DelayS(2); /* 2 sec delay */ Send2Gsm("AT+CMGF=1\r\n"); wait for 2 sec; -- Switch to text mode */ DelayS(2); /* 2 sec delay */ Send2Gsm("AT+CMGS=\"+919447367176\"\r\n"); wait for 2 sec; -- Send SMS to a cell number */ DelayS(2); /* 2 sec delay */ Send2Gsm("TEST DATA FROM RhydoLABZ-COCHIN"); wait for 2 sec; -- Input SMS Data */ SerialTx(0x1a); /* Ctrl-Z indicates end of SMS */ DelayS(2); /* 2 sec delay */ wait; end process main;  

Kevin

[Altera_Forum]

the code above cannot be synthesised as it contains a wait statement, which are used in simukation only.

[Altera_Forum]

Hi, 

 Please answer the following questions  1. Why do you need to convert a C program into VHDL? Instead use NIOS II soft core processor to run the C code. That would save your time.  2. Which FPGA are you targeting?  Regards, Ritesh

[Altera_Forum]

--- Quote Start ---  the code above cannot be synthesised as it contains a wait statement, which are used in simukation only.  --- Quote End ---  Synthesis was not stated as a requirement. No need to make a simple request more complicated than actually requested.  Kevin

[Altera_Forum]

--- Quote Start ---  the code above cannot be synthesised as it contains a wait statement, which are used in simukation only.  --- Quote End ---    That wasnt the request - the OP wanted VHDL. KJ Posted Legal VHDL.

[Altera_Forum]

coz i work in project called rfid and gsm mobile secuirty system and this based on fpga and vhdl 

 fpga :altera DEO board

[Altera_Forum]

My reply about the code not being synthesizable was intended as a note, just something to keep in mind. I should have stated this. 

 If you don't want to use a softcore like NiosII you will have to think about which hardware components you need. I see an rs-232? and depending on the devices you use to send the GSM signals you will need to implement an interface for this as well.

[Altera_Forum]

There can be two ways for the implementation: 

 1. Design a NIOS II System with RS232 , SPI and other peripherals. Port your C code & libraries to NIOS II processor (though this may not be straight forward). Compile & generate the binaries.   2. Complete RTL implementation For this you need to write VHDL code for UART, SPI protocol. Assuming this is a college project, implementing SPI & UART code in RTL can be mini project in itself. So divide the task & then integrate the modules where in top file you will have the Sequence of function calls (Algorithm for Security System).  Regards, Ritesh

[Altera_Forum]

As you want VHDL only, which I think you want based on this thread: 

http://www.alteraforum.com/forum/showthread.php?t=52376 You will have to go with b.riteshes option 2.   To which I want to addd the suggestion to use a state machine to control the system you are building.