Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15329 Discussions

illegal inout port connections in vsim 3053

Altera_Forum
Honored Contributor II
910 Views

While simulating my Verilog testbench I get this error on ny inout ports. What datatypes should they be so that I don't get this error. Also I am assigning some of these inouts in initial blocks; how should I do? 

 

Please advise. Many thanks
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
115 Views

Post the code, so we can have a look.

Reply