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illegal inout port connections in vsim 3053

Altera_Forum
Honored Contributor II
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While simulating my Verilog testbench I get this error on ny inout ports. What datatypes should they be so that I don't get this error. Also I am assigning some of these inouts in initial blocks; how should I do? 

 

Please advise. Many thanks
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Altera_Forum
Honored Contributor II
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Post the code, so we can have a look.

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