Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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internal osc & global clk

s002wjh
New Contributor I
926 Views

is there way to get the internal osc on cyclone 3 or 4 use the global clk network?  if so whats the .qsf command for that?  i think the 80mhz internal osc is not using the global clk network.

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SyafieqS
Employee
915 Views

Hi Wen,


You may need to refer to KDB below on how to do the assignment for the GCLK,PCLK,RCLK etc.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd09282011_171.html


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s002wjh
New Contributor I
912 Views

so if timing my constraint is like this

create_clock -name "div2_clk" -period 25.000 [get_registers {frequency_divider:frequency_divider_inst|clk_div2}]


create_generated_clock -divide_by 2 -source [get_registers {frequency_divider:frequency_divider_inst|clk_div2}] -name div4_clk [get_registers {frequency_divider:frequency_divider_inst|clk_div4}]

 

do i need write something like this? for global clk network?  i divide the internal  osc by 4

set_location_assignment CLKCTRL_G2 -to "get_registers {frequency_divider:frequency_divider_inst|clk_div4}~clkctrl"

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SyafieqS
Employee
869 Views

Hi Wen,


May I know if the KDB given able to assign the internal oscillator to GCLK? Alternatively, in assignment editor, you can select global signal and assign global clock to the osc and you can reflect in your qsf.


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