Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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internal osc timing const

s002wjh
New Contributor I
908 Views

using the internal osc 80mhz "altint_osc" ip then divide by 2 to drive my logic, but it output warning  even after i put the clk constrain.  any help?

 

create_clock -name int_clk -period 25ns   [get_ports {frequency_divider:frequency_divider_inst|clk_div2}] 

clk_div2 is output reg

 i also try get_pins & drive_clock_uncertainty didnt help with the warning

Warning (332060): Node: frequency_divider:frequency_divider_inst|clk_div2 was determined to be a clock but was found without an associated clock assignment.

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sstrell
Honored Contributor III
862 Views

You don't mention which device, but an internal clock gets constrained with create_generated_clock, not create_clock.

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s002wjh
New Contributor I
833 Views

for some reason get_pins doesn't work.  i had to use get_registers for my divider to set timing

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Kenny_Tan
Moderator
822 Views

thanks, good to know this.


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Kenny_Tan
Moderator
787 Views

Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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