Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15340 Discussions

keeping signals for signaltap, even if not used in the design

PhilipJ451
Beginner
226 Views

Hi,

can anybody advise me of a method to keep signals even if they are not used in the design? e.g. I am currently debugging some FIFOs which have an output that is the number of characters in the FIFO (rdusedw and wrusedw).

My actual design doesn't need to use them but it would be useful to display them in a SignalTap when debugging but Quartus removes them and I simply can't find the nodes in SignalTap.

I have tried the attributes keep, preserve and noprune but none of them work

Any advice would be much appreciated

PhilipJ

 

0 Kudos
2 Replies
sstrell
Honored Contributor III
220 Views

If these are signals in your RTL code, connecting them up as pre-synthesis signals in the Signal Tap node list automatically preserves them through compilation.  Make sure you set the filter when selecting them in the Node list (double-click in the Node list to open the Node Finder to do this) as "Signal Tap: pre-synthesis".

#iwork4intel

PhilipJ451
Beginner
213 Views

Hi,

thanks for the tip.

The design is based upon the IP Catalog FIFO and when I first looked at the element "MyFIFO" the signal I wanted wasn't there, even as pre-synthesis, but I drilled down into the actual IP element "MyFIFO:FIFO1" I found the signals.

Still so much to learn!!

PhilipJ

 

Reply