Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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keeping signals for signaltap, even if not used in the design

PhilipJ451
Beginner
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Hi,

can anybody advise me of a method to keep signals even if they are not used in the design? e.g. I am currently debugging some FIFOs which have an output that is the number of characters in the FIFO (rdusedw and wrusedw).

My actual design doesn't need to use them but it would be useful to display them in a SignalTap when debugging but Quartus removes them and I simply can't find the nodes in SignalTap.

I have tried the attributes keep, preserve and noprune but none of them work

Any advice would be much appreciated

PhilipJ

 

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sstrell
Honored Contributor III
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If these are signals in your RTL code, connecting them up as pre-synthesis signals in the Signal Tap node list automatically preserves them through compilation.  Make sure you set the filter when selecting them in the Node list (double-click in the Node list to open the Node Finder to do this) as "Signal Tap: pre-synthesis".

#iwork4intel

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PhilipJ451
Beginner
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Hi,

thanks for the tip.

The design is based upon the IP Catalog FIFO and when I first looked at the element "MyFIFO" the signal I wanted wasn't there, even as pre-synthesis, but I drilled down into the actual IP element "MyFIFO:FIFO1" I found the signals.

Still so much to learn!!

PhilipJ

 

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