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keeping signals for signaltap

nicoh
Beginner
674 Views

Hi,

 

I'm using Quartus prime lite edition (language VHDL).

how can I "keep" signals so they appear in the siganltap search? 

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ShengN_Intel
Employee
606 Views

Hi,


May be can try with attribute noprune check this https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_noprune.htm, adding virtual pins in the Assignment Editor or use "pre-synthesis" filter in SignalTap's node selector and tapped the signal inside a "component" rather than in the top-entity where it is generated.


Thanks,

Best regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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sstrell
Honored Contributor III
658 Views

If you want to preserve signals to tap as post-fit signals, you can use the "keep" and/or "preserve" synthesis attributes in your HDL code.  There is a preserve for debug feature that uses project assignments, but that's only in the Pro edition of the tool.  You can also just tap the signals pre-synthesis, basically tapping the signals directly from your RTL code.

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nicoh
Beginner
645 Views

I tried the "keep" and/or "preserve" (I always look for pre-synthesis) and doesn't work.. 

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sstrell
Honored Contributor III
641 Views
What exactly are you trying to tap?
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nicoh
Beginner
639 Views

some internal signals in my project (flag, counter, etc) 

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ShengN_Intel
Employee
607 Views

Hi,


May be can try with attribute noprune check this https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_noprune.htm, adding virtual pins in the Assignment Editor or use "pre-synthesis" filter in SignalTap's node selector and tapped the signal inside a "component" rather than in the top-entity where it is generated.


Thanks,

Best regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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