I'm new to Quartus and I'm trying to read back an elaborated design from quartus_syn, however when I run the 'load_rtl_netlist' I get the following error:
ERROR: Can't read compiler database. Run the Analysis and Synthesis (quartus_map) successfully before using this command.
My flow is the following
- Create project using the 'project_new ...' command
- Set the top module and load the RTL files
- Run analysis and elaboration using 'execute_flow -analysis_and_elaboration'
- Call 'load_rtl_netlist'
I can execute steps 1-3 without issues, but I get errors when loading the netlist. Is there any step that I'm missing?
I'm running Quartus Prime Pro 184.108.40.206
Can you explain why you need to run this command? You can simply synthesize the design (as the error says) and then use tools based on the post-synthesis netlist like the RTL Viewer.
I have reported this to our developer. You may use GUI: Tools > Netlist Viewers > RTL Viewer as a workaround at the moment.
I'd like to run this command so that I can port my automation scripts from the xilinx environment. Is there any other command I could use to perform RTL search operations? Things like [get_ports ...], [get_clocks ...] etc?
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