load_rtl_netlist can't read compiler database

[Diego2]

Hello

I'm new to Quartus and I'm trying to read back an elaborated design from quartus_syn, however when I run the 'load_rtl_netlist' I get the following error:

ERROR: Can't read compiler database. Run the Analysis and Synthesis (quartus_map) successfully before using this command.

My flow is the following

1. Create project using the 'project_new ...' command
2. Set the top module and load the RTL files
3. Run analysis and elaboration using 'execute_flow -analysis_and_elaboration'
4. Call 'load_rtl_netlist'

I can execute steps 1-3 without issues, but I get errors when loading the netlist. Is there any step that I'm missing?

I'm running Quartus Prime Pro 19.4.0.64

Thanks!

[sstrell]

Can you explain why you need to run this command?  You can simply synthesize the design (as the error says) and then use tools based on the post-synthesis netlist like the RTL Viewer.

[KhaiChein_Y_Intel]

Hi,

I have reported this to our developer. You may use GUI: Tools > Netlist Viewers > RTL Viewer as a workaround at the moment.

Thanks

Best regards,

KhaiY

[Diego2]

Thanks

I'd like to run this command so that I can port my automation scripts from the xilinx environment. Is there any other command I could use to perform RTL search operations? Things like [get_ports ...], [get_clocks ...] etc?

Regards,

Diego

[KhaiChein_Y_Intel · Accepted solution]

Hi,

You may check the available command for each Quartus executables here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/tclscriptrefmnl.pdf

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Thanks

Best regards,

KhaiY