Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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mm_interconnect generation for system with PCIe EP, HBM2 Controllers and AXI interface IPs

SivaKona
Employee
162 Views

Hi ,


I am trying to build a system with PCIe EP, HBM2 Controllers and AXI interface IPs.
But facing issues with Address Mapping for slaves.

 

HBM Address Range : 0x0_0000_0000 to 0x1_FFFF_FFFF (32 instances of 256MB HBM slices)

DUT Address Range : 0x2_0000_0000 to 0x2_00FF_FFFF

HOST System Memory Address Range  : 0x4_0000_0000 to 0x5_FFFF_FFFF

 

Q) I have set the Slave port Address widths at 38 bits for all the slaves. Is this a correct method, Or do I need to set the address port width as the slave Address range(e.g, 24 bits for my DUT)?

 

I am using one AXI Master BFM and one AXI Slave BFM to build mm_interconnect. 

Is there a way to use Blackbox components to build mm_interconnect in Quartus Platform Designer? If yes , Please share the procedure. 

 

Quartus Version: quartus_prime_pro/21.2.0.72

 

Regards

Siva Kona

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1 Solution
SivaKona
Employee
111 Views

Hi,

I could resolve this issue after few experiments.

Regards

Siva Kona 

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1 Reply
SivaKona
Employee
112 Views

Hi,

I could resolve this issue after few experiments.

Regards

Siva Kona 

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