Does anyone know if there is something in modelsim or through quartus to dump contents of memory blocks used within design after synthesis. There is a way to view memory once you download design on the FPGA to view memory contents but not in source or just synthesis (without downloading to FPGA). I am using M4K blocks for my ram.
You can ask for post synthesis simulation netlist dump (VO, VHO, etc. Under EDA settings) then open it up in an editor and search for the RAM by name. It will have a pointer to a MIF or HEX file with the contents.
