modlesim 6.6d

[Altera_Forum]

i am new to modlesim, i downloaded the latest version, i hope if someone tells me how to simulate vhdl program with modlesim in simple way

[Altera_Forum]

Use these commands in the command window, or in a .do file: 

 vcom <my_vhdl_file> vsim <my_entity> run 1ms

[Altera_Forum]

thanks for the reply,  

how can i enter some vlaues to my inputs to see the repose of the outputs in modlesim

[Altera_Forum]

You need to write a testbench in HDL.

[Altera_Forum]

is there any way we can force the inputs to be 1 or 0 and see the output, if not how to write testbench in HDL

[Altera_Forum]

you can only do inputs via a testbench. 

A testbench is just an HDL file, like any other, that instantiates your unit under test.

[Altera_Forum]

how to write this HDL file, is it done by the modlesim, or i have to create it, is there any information may help me in this

[Altera_Forum]

Its just a text file. What language is your design in?

[Altera_Forum]

if you mean the vhd file that i am simulating, it is already created and i am simulating it , or u mean different file beside the VHDL code program with extension vhd

[Altera_Forum]

the testbench is a completly separate VHDL file from your design - used only for the purpose of testing. Because it will not get synthesised, you can do all sorts of things you would otherwise not be allowed to do. 

 For example, to generate a clock, you can do this:  --100 MHz clock signal clk : std_logic := '1'; ... clk <= not clk after 5 ns;  you then create the other input signals however you want and connect them to the design under test, and then run the testbench in Modelsim.  I think Quartus can create a testbench for you, but I usually just create them myself.

[Altera_Forum]

THE program written in VHDL codes by using quartusII

[Altera_Forum]

I suggest you ask more specific questions. You can write the testbench in quartus but you cannot compile it in there.

[Altera_Forum]

i think there is a way where we can force some inputs and see the outputs in modlesim

[Altera_Forum]

No there is not. 

 The old quartus simulator allowed that, but that is not included in Quartus 10+

[Altera_Forum]

i can see it in modlesim after selecting new source , but do i need to write all the possible inputs

[Altera_Forum]

I suggest you focus your questions more clearly - it is not very clear what you are talking about.

[Altera_Forum]

my question is, as i have VHDL codes that are working fine and i simulated then in quartus ii, and i used the waveform file in quartus , it works fine 

i want to use modlesim to simulate the same vhdl code(program), so as i did in quartus i selected some values to the inputs and observed the output response.. is there a way i do the same in modlesim, putting some input values and see the outputs,

[Altera_Forum]

Like I said, the old quartus simulator supports what you are trying to do. You may be able to export this as a file Modelsim can understand, but usually you create another VHDL file as the testbench for modelsim. 

 If you think they are working fine using the quartus simulator, why do you want to use modelsim?

[Altera_Forum]

i want to work with modlesim, and try it,,, do u know to create this test bench for modlesim, is there automatic way

[Altera_Forum]

You can also refer to the following user guide to create stimulus waveform using modelsim waveform editor. 

 http://www.altera.com/literature/ug/ug_gs_msa_qii.pdf?gsa_pos=19&wt.oss_r=1&wt.oss=waveform editor   For a design with complicated simulation, I would recommend you to create a testbench.