Hello! I am working with Cylcon IV FPGA, in Verilog, in Quartus 19.
Can someone please tell me how to work correctly (add, subtract, divide, etc.) with multi-bit signed numbers if the input number has a certain bit depth, let's say [13:0] , and the output number is much larger, let's say 100 times larger.
In more detail. I get a 14-bit signal from an ADC, which enters the FPGA with the "clock" frequency, and I want to recalculate it to another number using a formula. Both the input of the output of the formula can be either a negative or a positive number. In this case, the output number can be 100 times larger than the input (this formula simulates the ADC signal amplifier), i.e. its bit depth must be at least 7 bits larger. The output signal at a given clock cycle depends on both the input signal at this clock cycle and the input and output signals at several (two) previous cycles.
Following is my code (partially):
input signed [13:0] signal_in,
output signed [13+7:0] signal_out, //(output depth is 7 bits higher than the input )
reg signed [13:0] inputsig [2:0]; // creating buffer/memory for previous cycle INput
reg signed [13+7:0] outputsig [2:0]; // creating buffer/memory for previous cycle OUTput (output depth is 7 bits higher than the input depth)
always @ (posedge clock)
inputsig<=signal_in; / / I use serial memory to put the INput signal there in order to store it for the previous 2 cycles
outputsig<=signal_out; / / I use serial memory to put the OUTput signal there in order to store it for the previous 2 cycles
assign y1B = (outputsig)*2'd2*alpha/12'd100; // alpha - is a fraction (0.98), that's why I make it a whole number (98), and then divide the term by 100
assign y2B = (outputsig)*alpha/12'd100*alpha/12'd100;
assign X0A = signal_in;
assign X1A = (inputsig)*alpha/12'd100 + (inputsig)*alpha/tau*T/12'd100; // задал 4 слагаемых, определяющих выходной сигнал
assign signal_out = (y1B - y2B + X0A - X1A); // here I add the above-set term to get the final formula for the output signal
The question is how to correctly switch from a signed 14-bit input number to a (7 + 14) bit signed number so that the formula would work? Am I multiplying by alpha and dividing by 100 correctly? So far, whatever I did, it gives me some kind of garbage out... I will be grateful for any help!
- FPGA arithmetics