need help syntax with sdc

Altera_Forum · ‎07-04-2016

hi,

i get a problem working with sdc, i think it's only a syntax one.

my top is :

     
u1 : enet_rx_clk_pllport map(
inclk0        => enet_rx_clk,
c0            => enet_rx_clk_270deg,--0  
c1            => enet_tx_clk_mac, --90
c2            => enet_tx_clk_phy,--180
locked        => open
);

and sdc is like :


create_clock -period 8 -name "ENET0_RX_CLK" 
derive_pll_clocks
create_generated_clock -name tx_data_clock -source   
create_generated_clock -name pll_output_tx -phase 90 -source

At fitter, it says : Warning (332174): Ignored filter at test_0.sdc(25): test_0|u1|c0 could not be matched with a pin

I hope someone could help me,

cheers

Altera_Forum · ‎07-05-2016

Hi,

usually you don't need constrain the generated clocks if you use "derive_pll_clocks". To get the proper syntax I'm using Timequest. Just start Timequest and create the timing netlist. Then type at TCL console "derive_pll_clocks". Now you will see the correct commands.

Jens

Altera_Forum · ‎07-05-2016

ok thank you, ill try this