no setup paths were found in quartus by Report timing

[Jing_x]

hi,

I am doing the constrains for the 1000 base T1 eth. In the receiving path, FPGA get rx clock and center aligned ddr data. i use the  altddrio primitive to capture the ddr data. The fpga is cyclone V.

I  create a 90 degree shift virtual clock and set the input delay. By add addtional Programmable IOE Delay D1, the design already worked.

I met several problem by the timing report for the above case:

1. when I try reporting timing for the input signal, i want the check the setup and hold up slack for the altddrio. I get the massage as follow:

It seems there is no register path detected. it happens also for the hold up report. I also set falsh path like this:

    set_false_path -fall_from [get_clocks $rx_clock_virt] -rise_to [get_clocks $rx_clock] -setup

    set_false_path -rise_from [get_clocks $rx_clock_virt] -fall_to [get_clocks $rx_clock] -setup

    set_false_path -fall_from [get_clocks $rx_clock_virt] -fall_to [get_clocks $rx_clock] -hold

    set_false_path -rise_from [get_clocks $rx_clock_virt] -rise_to [get_clocks $rx_clock] -hold

2. Because the delay by IOE D1 needs to be added in the project qsf file, I try to set a general constrains that can be reused convenient also by other projects without changing the qsf file. I want to move this delay to the constrain file by the input delay, I increase the input delay based on the following table:

Then the design doesn't work. It this idea correct? If yes, how should I do this? 

[ShengN_Intel]

Hi,

1.You can't find the setup and hold up slack for the altddrio most probably because of the center aligned set_false_path. However I think it should be okay. If remove those set_false_path, able to see the setup and hold slack?

2.You can only set IOE in assignment editor check that document link https://www.intel.com/content/www/us/en/docs/programmable/683801/current/programmable-ioe-delay.html

You can set this value in the Intel® Quartus® Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi,

May I know any further update or concern?

Thanks,

Regards,

Sheng