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I am very rusty in VHDL and I have the following problem. I am testing to inputs for '1' and if either one of them is high I assign the output a '1'. However when I do this the output is always 'X'. I am sure I do something absolutely stupid, but I can't figure it out. Sorry for such a trvial problem.
Here is the screen shot http://www.alteraforum.com/forum/attachment.php?attachmentid=13101&stc=1 And here are the wto codes, the source file and the testbenchLink Copied
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Hi pabloemma,
In line 66 of test_timeTB.vhd, process "init" drives "00" to "F_DOUT_L". So if now your instance of test_time tries to drive anything other than zeros to that signal, you get a conflict, which resolves to an 'X'. Remove line 66 and it should be fine. Best regards, GooGooCluster- Mark as New
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Thanks, sorry it took a while to respond. I am on travel.
andi
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