parameter passing for IP in Platform Designer (Qsys)

[MSchn21]

I have a design which was originally done in Quartus 15.1.  We passed some parameters into QSys (now Platform Designer) for configuration of the altera_pcie_256_hip_avmm IP.  I have recently moved the design forward to version 19 but get errors that seem to imply that I either can’t pass parameters into QSys anymore or that maybe the parameter name changed.

The original code had the PCIe_DEVID defined as a parameter in a wrapper verilog file.  Later on in the same verilog file, there is a defparam followed by the instantiation of the qsys system.  This worked for Quartus 15 but does not work for Quartus 19

defparam u0.PCIE_DEVID=PCIE_DEVID

mySystem_qsys  u0 (

// port connections

)

Inside the qsys system is the altera_pcie_256_hip_avmm  IP which has the field for the PCI device ID that I am trying to set.

The error I receive is: 

"12077 Node instance "u0" instantiated with unknown parameter "PCIE_DEVID".

Its almost as if either the name of the parameter field changed in the IP block or maybe defparam has been deprecated.  I tried using Instance Parameters for passing into the qsys system that was unsuccessful.

Can you help me with the proper syntax to accomplish what used to work with Quartus 15?

Thanks.

[SengKok_L_Intel]

What is this device? Are you using AVST or AVSM?

Regards -SK

[MSchn21]

The device is Stratix V and the bar space interface is memory mapped.  I don't think these matter.  I contacted local FAE about the issue.  They are checking on whether it is possible to pass parameters into an instantiated QSys system.  Our prior workaround has been to post-process the synthesized verilog file that is created after QSys generation step.  The post-processing adds code for the parameters.  FAE is checking to see if there is a more elegant way than post-processing with script.

[SengKok_L_Intel]

Hi,

This is glad to see there is good progress and the FAE is helping you now.

Regards -SK

[SengKok_L_Intel]

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