pcie gen3x8 DMA EndPoint with HPTXS path is not meeting timing

[SivaKona]

Hi , 
I have generated an FPGA model with PCIe DMA EP and onchip Memory as shown in the  attached "DMA_EP_OnchipMem_model.png" file.
I have instantiated an Onchip Memory of size 16MB.
Seeing Setup violations due to large Routing delay's as shown in the "Setup_viol_Data_Path.png" 

What is the ideal method to fix these Setup violations?

Regards
Siva Kona

[SivaKona]

I realized that the longer IC (Inter Connection) delays are due to the paths to farther Block RAMS blocks.
When I reduced OnChip memory size from 16MB to 2MB , The design met Setup time.

Is there a way close timing without reducing the  Block RAM usage?

Regards

Siva Kona

[wchiah]

Hi,

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best regards,

Wincent_C_Intel

[RichardTanSY_Intel · Accepted solution]

You may try to lower your clock frequency, with increased in clock period, it is easier to meet setup.

Or you can add pipeline stages. You may checkout the video below

https://www.youtube.com/watch?v=g6SjVhVderc

[RichardTanSY_Intel]

Do you have further question in regards to this case?

[RichardTanSY_Intel]

I’m glad that your question has been addressed.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution. 

[SivaKona]

Hi Richard Tan
I do not have any further follow up questions. Thank You