platform designer generation

[Gauthier_Auvray]

Hi,

I would like to use the "generate tcl file for project" feature to be able to re-create and build a project on a CI system (the design uses Platform Designer).

1. I can generate the TCL file of the project with "Project-> Generate TCL File for Project"

2. In the generated TCL file I add .qsys file (platform designer), instead of .qip file

3. I can rebuild the project by sourcing the TCL file with quartus_sh

4. When I then start the compilation flow, Quartus first generates the Platform Designer system in the db folder. Then it fails indicating that the library does not contain the Platform Designer system

(see attached file)

What is the right way to do that?

Thanks,

Gauthier

[Gauthier_Auvray]

Hello, after changer the IP settings HDL preference to VHDL it worked.

The next question is: how can we set this parameter in older Quartus version? (Quartus 12/13). It seems only accessible from QSYS tool.

Thanks,

Gauthier

[FvM]

Hello,

by using VHDL instantiation syntax "entity <library>.<component>", you need IP components generated in VHDL.

Global parameter HDL_PREFERENCE has been introduced in Quartus 17 as far as I'm aware of. Most simple solution is probably to regenerate the IP HDL manually, chosing the respective language.

Regards,
Frank

[Gauthier_Auvray]

OK thanks! I will use explicit component declaration to instantiate verilog in VHDL file.

[ShengN_Intel]

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