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possiblity of unstable reset lead to misoperation

WNC_HowardHuang
Beginner
529 Views

Hi,

There's a problem that makes us confus.

The input reset signal is like this

WNC_HowardHuang_0-1672135633734.png

The unstable part would stay about 40 ms long.

Here's our source code for trigger

WNC_HowardHuang_0-1672189250399.png

Here's the waveform in SignalTap

WNC_HowardHuang_2-1672189598220.png

When sig_A & sig_B is all 0

edge_sig should be 0

But sig_intr appear a pulse when doing reset

Will this situation because of the unstable of reset?

BTW, we also disscuss about the possiblitiy of synchonus reset woule influence sig_intr problem,

 but we are not sure if this would be the problem after synthesis or not.

Thanks.

 

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6 Replies
sstrell
Honored Contributor III
510 Views

It certainly could be because of the unstable pulse.  Signal Tap can't help with capturing an issue like that.  Check your timing analysis.  What does your .sdc look like?

But stranger is that there is no way in your design for sig_A to ever go high.  Typo in your reset process?

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WNC_HowardHuang
Beginner
486 Views

Hi,

Thanks for your replay.

In our design, there's only have clock in .sdc file

create_clock -name CLK25M -period 40.000 -waveform { 0.000 20.000 } [get_ports {FPGA_25M}]
I think there's no error with reset process because reset signal is from outside FPGA.
 
We'll looking forward to this problem.
Thanks.
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FvM
Valued Contributor III
506 Views
In addition, what's the reset source? In case it's asynchronous to clock, you urgently need a reset synchronizer to achieve predictable behaviour.

Regards
Frank
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WNC_HowardHuang
Beginner
486 Views

Hi,

Thanks for your replay.

The source of reset is from the other CHIP outside FPGA.

We guess the unstable waveform might be caused by PCB layout.

 

We tried to synchronus reset using shift register

Then replace original procedure reset part by higher bit of shift register

So far, the test result seem fine.

 

But we think the best way to solve this problem is to figure out the unstable problem of reset.

 

Thanks.

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SyafieqS
Moderator
478 Views

Higher bit shift register might be a good temporary workaround. But you still need to root cause from outside for unstable pulse. Afraid might cause another issue.


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SyafieqS
Moderator
396 Views

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