problem with an addition in a vhdl code

[Altera_Forum]

Hello, 

 I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically, I take that the output nn is equal to 1.. At first I had that my signals and the output are this type: "sfixed" beacause I wanted to add fixed point numbers but then the following error was appeared: expression has 7 elements, but must have 6 elements Then I increased the number of elements and it appeared this error: expression has 8 elements, but must have 7 elements   LIBRARY ieee; USE ieee.std_logic_1164.all;   library ieee_proposed; use ieee_proposed.fixed_pkg.all; use ieee.numeric_std.all; USE ieee.std_logic_signed.all;   ENTITY adder IS  PORT (z:IN SIGNED(2 DOWNTO 0) :="001";  nn:OUT signed (5 DOWNTO 0)); END adder;   ARCHITECTURE behavior OF adder IS signal met:signed(5 DOWNTO 0); signal monada:signed(2 DOWNTO 0); signal meta:signed(5 DOWNTO 0);   BEGIN  PROCESS(met) -- variable count: integer range 26 downto 0;     BEGIN   --monada <= to_sfixed (1,monada); FOR i IN 1 TO 25 LOOP    met <=met+1; -- met <=meta; END LOOP;      FOR i IN 1 TO 5 LOOP  IF(z=i) THEN  nn<=met;  END IF; END LOOP;   END process;   END behavior;     What is my error?What I have to do?Please help me!!Thank you very much in advance..

[Altera_Forum]

I dont know which line you're talking about has an error, because you dont point it out. 

 But I suspect the initial problem comes from your for loop. A signal is only assigned when a process suspends. So in your code, met <= met + 1; occurs 25 times, but as the signal wont be updated, it is just a single + 1, not 25x +1.   So can you please rephrase your question, with the problem marked in your code.

[Altera_Forum]

The line reported to cause problems can't be found in the code. 

 Presently, the code sets an output value nn according to input z. But signal met isn't initialized in the process, so the output will be undefined.

[Altera_Forum]

Sorry I made a mistake when I reported the line. 

The line that I wanted to refer is this:met <=met+1; With this code I wanted to do the addition operation. I wanted the variable 'met' to be zero when we insert in the loop  FOR i IN 1 TO 25 LOOP met <=met+1; END LOOP;  and then to be increased so as finally to be equal to 25. This is a simple code that I tried to do because I try to write a code and there the variable 'met' is a fixed point number and I added it with a fixed point number.

[Altera_Forum]

--- Quote Start ---  and then to be increased so as finally to be equal to 25.  --- Quote End ---   No, it's not initialized to 0, and not counting up, as Tricky explained.    --- Quote Start ---  This is a simple code that I tried to do because I try to write a code and there the variable 'met' is a fixed point number and I added it with a fixed point number.  --- Quote End ---   It's defined as signed, not fixed point.  You should also get rid of conflicting libraries.

[Altera_Forum]

Yes I know that here the variable met is defined as signed. 

I thought that if I do not initialize a variable then it is equal to 0.  According to Tricky it did not increased because met is a signal. What should I do so as to be increased?In which type should I define it?

[Altera_Forum]

From this code - I guess you have a software background? 

There is a major problem with the code in that the process is sensitive to a signal that is updated inside itself - so this process will just run in an infinite loop in simulation and you'll probably hit the iteration limit.  Initialisation is that - the value given to a signal/variable when the simulation is started. In your code, it has no initialisation value, so as the signed type is an array of std_logic it will initialise to "UUUUUU" (uninitialised) as per the type definition (uninitialised values take the leftmost value).  If you want to increase this value by 25, why not simply write:  met <= met + 25?  I suggest you go back to a VHDL tutorial, preferably one that talks about digital logic too. If your digital logic knowledge is lacking - I suggest you read up on that to. When you're more confident, draw your circuit out on paper. HDL stands for hardware description language, so if you dont know what the circuit should be, how do you expect to describe it?

[Altera_Forum]

Thank you for your helpful information. 

I do not write: met <= met + 25 because I want to increase the variable 'met' step by step. Specifically I want 'met' to take the values 1 then 2 then 3 and etc and this is the reason that I use the the loop in my code.

[Altera_Forum]

--- Quote Start ---  Thank you for your helpful information. I do not write: met <= met + 25 because I want to increase the variable 'met' step by step. Specifically I want 'met' to take the values 1 then 2 then 3 and etc and this is the reason that I use the the loop in my code.  --- Quote End ---     I think you should use "vector" signals instead of sign or unsign. Also you were designing circuit using HDL code insdead of writing c code! So you should make a clock involve in your hardware codes, and design synchronized circuit.

[Altera_Forum]

--- Quote Start ---  I think you should use "vector" signals instead of sign or unsign.   --- Quote End ---    A signed/usnigned is a vector type. and is perfectly suitable here.    --- Quote Start ---   I do not write: met <= met + 25 because I want to increase the variable 'met' step by step. Specifically I want 'met' to take the values 1 then 2 then 3 and etc and this is the reason that I use the the loop in my code.   --- Quote End ---    Then you would not use a for loop. loops unrol into parrallel logic. You need a clock. And a good VHDL tutorial (I think you need to go back to step one and start again. Writing VHDL is NOT like writing C)