I have an issue with L-Tile/H-tile Tranceiver ATX PLL Intel stratix IP, when integrated, the ppl locked output is not asserted. Is there any known problems for this ip or some setting that affects this functionality? I use it in PLL mode feeding two GTX channels, with one reference an one output clock without reconfiguration I/f
As I understand it, you are observing ATX PLL unlock issue in S10 devices. The PLL lock signal seems not asserted. Based on my understanding, there is no known issue with the pll_locked signal. We would require further debugging to tell what might be wrong.
For your information, generally the ATX PLL lock issue might relate to reset sequence, refclk and calibration. Prior to hardware debugging, just would like to check with you if you have had a chance to perform a Modelsim simulation with your design to see if similar issue is observed? This would be helpful to isolate any functional related issue.
Specific to reset, just would like to check with you if you are connecting the ATX PLL to the XCVR reset controller? The reset controller will take care of the required reset sequence to ensure the ATX PLL and XCVR channels can work as expected.
Specific to refclk, would you mind to probe or check the signal integrity of the refclk signal using oscilloscope and cross check with the refclk specifications in device datasheet to ensure all the specifications are met? Also, I believe you have already done so but just to isolate out this. Please help to double check on the refclk frequency setting in ATX PLL and the frequency from the oscillator using scope.
Specific to the calibration, we would require the refclk of ATX PLL and OSC_CLK_1 to be stable and free-running prior to device power up. This is to ensure proper power up calibration for the ATX PLL. In addition to this, please help to ensure the RREF pin is connected to 2k Ohm resistor to GND.
Please let me know if there is any concern. Thank you.