Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Honored Contributor I
2,456 Views

problem with simulation waveform editor

hello to everyone! i am a quartus II newbie. My first exercise on this program is to build an EXOR port. After having connected everything i started compilation which was succefully completed. After this i started simulation waveform editor and i create a waveform. Saved everithing and started a functional simulation. It cannot be finished due to two errors. IMPORTANT: i'm running quartus II on parallel Desktop because i have a Macbook pro and a 32bit win-7 pc which doesn't allow me to work with quartus II. Here attached the simulation flow progress: 

 

Determining the location of the ModelSim executable... 

Using: c:/altera/14.1/modelsim_ase/win32aloem/ 

 

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options 

Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. 

 

**** Generating the ModelSim Testbench **** 

 

quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source="//psf/Home/Desktop/università/Digilab/1/uno.vwf" --testbench_file="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt" 

 

Info: ******************************************************************* 

Info: Running Quartus II 64-Bit EDA Netlist Writer 

Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition 

Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 

Info: Your use of Altera Corporation's design tools, logic functions  

Info: and other software and tools, and its AMPP partner logic  

Info: functions, and any output files from any of the foregoing  

Info: (including device programming or simulation files), and any  

Info: associated documentation or information are expressly subject  

Info: to the terms and conditions of the Altera Program License  

Info: Subscription Agreement, the Altera Quartus II License Agreement, 

Info: the Altera MegaCore Function License Agreement, or other  

Info: applicable license agreement, including, without limitation,  

Info: that your use is for the sole purpose of programming logic  

Info: devices manufactured by Altera and sold by Altera or its  

Info: authorized distributors. Please refer to the applicable  

Info: agreement for further details. 

Info: Processing started: Wed Mar 09 18:21:18 2016 

Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source=//psf/Home/Desktop/università/Digilab/1/uno.vwf --testbench_file=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt 

Warning (201007): Can't find port "y" in design 

Warning (201005): Ignoring output pin "y" in vector source file when writing test bench files 

Info (201000): Generated Verilog Test Bench File //psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt for simulation 

Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 2 warnings 

Info: Peak virtual memory: 599 megabytes 

Info: Processing ended: Wed Mar 09 18:21:19 2016 

Info: Elapsed time: 00:00:01 

Info: Total CPU time (on all processors): 00:00:01 

 

 

Completed successfully.  

 

Completed successfully.  

 

**** Generating the functional simulation netlist **** 

 

quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/" uno -c uno 

 

Info: ******************************************************************* 

Info: Running Quartus II 64-Bit EDA Netlist Writer 

Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition 

Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 

Info: Your use of Altera Corporation's design tools, logic functions  

Info: and other software and tools, and its AMPP partner logic  

Info: functions, and any output files from any of the foregoing  

Info: (including device programming or simulation files), and any  

Info: associated documentation or information are expressly subject  

Info: to the terms and conditions of the Altera Program License  

Info: Subscription Agreement, the Altera Quartus II License Agreement, 

Info: the Altera MegaCore Function License Agreement, or other  

Info: applicable license agreement, including, without limitation,  

Info: that your use is for the sole purpose of programming logic  

Info: devices manufactured by Altera and sold by Altera or its  

Info: authorized distributors. Please refer to the applicable  

Info: agreement for further details. 

Info: Processing started: Wed Mar 09 18:21:20 2016 

Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/ uno -c uno 

Info (204019): Generated file uno.vo in folder "//psf/Home/Desktop/università/Digilab/1/simulation/qsim//" for EDA simulation tool 

Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings 

Info: Peak virtual memory: 603 megabytes 

Info: Processing ended: Wed Mar 09 18:21:21 2016 

Info: Elapsed time: 00:00:01 

Info: Total CPU time (on all processors): 00:00:01 

 

 

Completed successfully.  

 

**** Generating the ModelSim .do script **** 

 

//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.do generated. 

 

Completed successfully.  

 

**** Running the ModelSim simulation **** 

 

c:/altera/14.1/modelsim_ase/win32aloem//vsim -c -do uno.do 

 

Reading C:/altera/14.1/modelsim_ase/tcl/vsim/pref.tcl 

 

# 10.3c 

 

 

 

# do uno.do# ** Warning: (vlib-34) Library already exists at "work".#  

 

# Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014# Start time: 18:21:22 on Mar 09,2016# vlog -work work uno.vo # init_dbinfo() DATABASE ERROR: (sqlite3_open //psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_lib.qdb): unable to open database file# mtilibWrite(): Unexpected null object encountered# ** Fatal: (vlog-9) Problem while writing token file "//psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_temp/vlog9ttz2d".# # The system cannot find the path specified. (GetLastError() = 3)# ** Error: uno.vo(32): Verilog Compiler exiting 

# End time: 18:21:22 on Mar 09,2016, Elapsed time: 0:00:00 

# Errors: 2, Warnings: 0 

# ** Error: c:/altera/14.1/modelsim_ase/win32aloem/vlog failed. 

# Executing ONERROR command at macro ./uno.do line 3 

 

 

Error.  

0 Kudos
3 Replies
Highlighted
Beginner
791 Views

I m having the same problem, can anyone help, below a piece of the information where the error appear:

# init_dbinfo() DATABASE ERROR: (sqlite3_open C:/Users/Bruno Otávio/Documents/FPGA/TesteModelsim/simulation/modelsim/rtl_work/_lib.qdb): unable to open database file

 

# mtilibWrite(): INTERNAL ERROR: Unexpected null object encountered

 

# ** Fatal: (vcom-9) Problem while writing token file "C:/Users/Bruno Otávio/Documents/FPGA/TesteModelsim/simulation/modelsim/rtl_work/_temp/vcomre2tad".

 

# O sistema não pode encontrar o caminho especificado. (GetLastError() = 3)

0 Kudos
Highlighted
Beginner
791 Views

Hi, I have the same problem:

 

**** Running the ModelSim simulation ****

 

C:/intelFPGA_lite/19.1/modelsim_ase/win32aloem/vsim -c -do casevirtual.do

 

Reading C:/intelFPGA_lite/19.1/modelsim_ase/tcl/vsim/pref.tcl

 

# 10.5b

 

 

# do casevirtual.do

 

# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016

# Start time: 22:48:47 on Apr 15,2020

# vcom -work work casevirtual.vho 

# -- Loading package STANDARD

# init_dbinfo() DATABASE ERROR: (sqlite3_open D:/ACER_WILSON/Ingeniería Electrónica Compartido/8° Semestre/Prototipado Rápido y VHDL/casevirtual/simulation/qsim/work/_lib.qdb): unable to open database file

# mtilibWrite(): INTERNAL ERROR: Unexpected null object encountered

# ** Fatal: (vcom-9) Problem while writing token file "D:/ACER_WILSON/Ingeniería Electrónica Compartido/8° Semestre/Prototipado Rápido y VHDL/casevirtual/simulation/qsim/work/_temp/vcom2erff3".

# El sistema no puede encontrar la ruta especificada. (GetLastError() = 3)

# ** Error: casevirtual.vho(30): VHDL Compiler exiting

# End time: 22:48:47 on Apr 15,2020, Elapsed time: 0:00:00

# Errors: 2, Warnings: 0

# ** Error: C:/intelFPGA_lite/19.1/modelsim_ase/win32aloem/vcom failed.

# Executing ONERROR command at macro ./casevirtual.do line 3

 

Error. 

 

I did solve it changing the directory of project.

The directory's name would be not contain special characters (like ticks or underscores)

0 Kudos
Highlighted
Beginner
269 Views

In case anyone finds this error message and wants to know the solution: all the previous users had accents in their project paths. ModelSim doesn't support them, just plain ASCII.

0 Kudos