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Altera_Forum
Honored Contributor I
1,398 Views

problem with type matching

Hey guys! 

 

I'm having a problem with component instantiation. I keep on getting the an error in modelsim that my types dont match up: # ** Failure: (vsim-3807) Types do not match between component and entity for port "addr_1".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 45# ** Failure: (vsim-3807) Types do not match between component and entity for port "addr_2".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 46# ** Failure: (vsim-3807) Types do not match between component and entity for port "xcol_write".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 52# ** Failure: (vsim-3807) Types do not match between component and entity for port "xrow_write".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 53# ** Failure: (vsim-3807) Types do not match between component and entity for port "xcol_read".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 54# ** Failure: (vsim-3807) Types do not match between component and entity for port "xrow_read".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 55# ** Failure: (vsim-3807) Types do not match between component and entity for port "xstate".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 58# ** Failure: (vsim-3807) Types do not match between component and entity for port "xtemp1".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 59# ** Failure: (vsim-3807) Types do not match between component and entity for port "xtemp2".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 60# ** Failure: (vsim-3807) Types do not match between component and entity for port "xtemp3".# Time: 0 ps Iteration: 0 Instance: /wvt_tb/UUT2 File: wvt.vho Line: 61 

 

I've checked like a thousand times and it is absolutely the same type between entity and component. I've also checked my libraries for multiple definitions, here are the libraries I use: 

library std;  

use std.textio.all; 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.std_logic_textio.all; 

use IEEE.NUMERIC_STD.ALL; 

 

I've noticed that all the errors are generated by integer types from the top entity (std_logics in the top entity and integer types in submodules dont generate the error). I know that the integers are converted to slv in the wvt.vho file to represent them physically but i've got no idea on how to deal with this. Here are the entity and component of the module in question:
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6 Replies
Altera_Forum
Honored Contributor I
65 Views

entity wvt is 

 

generic( 

data_width: integer := 8; 

image_size: integer := 32; 

addr_width: integer := 262144 

); 

 

port( 

clk :in std_logic; 

wvt_rst :in std_logic; 

start_up :in std_logic; 

fwvt_iwvt :in std_logic; 

finished_wvt :buffer std_logic; 

 

data_a :in std_logic_vector(data_width downto 0);  

data_b :in std_logic_vector(data_width downto 0); 

 

addr_1 :buffer integer range 0 to addr_width; 

addr_2 :buffer integer range 0 to addr_width; 

data_1 :out std_logic_vector(data_width downto 0); 

we_1 :out std_logic; 

data_2 :out std_logic_vector(data_width downto 0); 

we_2 :out std_logic; 

 

xread_write_flag: out std_logic; 

--xtemp_mem1: onedmem((image_size/2-1) downto 0); 

--xtemp_mem2: onedmem((image_size/2-1) downto 0); 

xcol_write: out integer range 0 to image_size; 

xrow_write: out integer range 0 to image_size;  

xcol_read: out integer range 0 to image_size; 

xrow_read: out integer range 0 to image_size; 

xstart_up_hold: out std_logic; 

xrow_col_switch: out std_logic; 

xstate: out integer range 0 to 4; 

xtemp1: out ieee.numeric_std.unsigned((data_width + 1) downto 0); 

xtemp2: out ieee.numeric_std.signed((data_width + 1) downto 0); 

xtemp3: out ieee.numeric_std.signed((data_width + 1) downto 0) 

); 

 

end entity;
Altera_Forum
Honored Contributor I
65 Views

component wvt is 

generic( 

data_width : natural := 8; 

image_size: integer := 32; 

addr_width: integer := 262144 

); 

 

 

port( 

clk :in std_logic; 

wvt_rst :in std_logic; 

start_up :in std_logic; 

fwvt_iwvt :in std_logic; 

finished_wvt :buffer std_logic; 

 

 

data_a :in std_logic_vector(data_width downto 0);  

data_b :in std_logic_vector(data_width downto 0); 

 

 

addr_1 :buffer integer range 0 to addr_width; 

addr_2 :buffer integer range 0 to addr_width; 

data_1 :out std_logic_vector(data_width downto 0); 

we_1 :out std_logic; 

data_2 :out std_logic_vector(data_width downto 0); 

we_2 :out std_logic; 

 

 

xread_write_flag: out std_logic; 

--xtemp_mem1: onedmem((image_size/2-1) downto 0); 

--xtemp_mem2: onedmem((image_size/2-1) downto 0); 

xcol_write: out integer range 0 to image_size; 

xrow_write: out integer range 0 to image_size;  

xcol_read: out integer range 0 to image_size; 

xrow_read: out integer range 0 to image_size; 

xstart_up_hold: out std_logic; 

xrow_col_switch: out std_logic; 

xstate: out integer range 0 to 4; 

xtemp1: out ieee.numeric_std.unsigned((data_width + 1) downto 0); 

xtemp2: out ieee.numeric_std.signed((data_width + 1) downto 0); 

xtemp3: out ieee.numeric_std.signed((data_width + 1) downto 0) 

); 

end component;
Altera_Forum
Honored Contributor I
65 Views

if you do netlist simulations, it is recomended that all ports from the DUT are std_logic_vector, as they will get converted to these when compiled. 

Otherwise, dont bother doing netlist sims, and keep to RTL sims (in 15 years, I have never needed to run a gate level sim).
Altera_Forum
Honored Contributor I
65 Views

I would say the same thing, using std_logic_vector instead of integer in your port list is a better practice. 

Of course you will probably have a few more cast operation but integer is not really HW friendly.
Altera_Forum
Honored Contributor I
65 Views

 

--- Quote Start ---  

I would say the same thing, using std_logic_vector instead of integer in your port list is a better practice. 

Of course you will probably have a few more cast operation but integer is not really HW friendly. 

--- Quote End ---  

 

 

This is only true if you really want to do netlist sims, or want to connect pins at the top level. 

Integer is perfectly hardware friendly for internal signals. I would always recommend an appropriate type for readable code over std_logic_vector. Even unsigned/signed can be used at the top level. 

 

Make your life easier with readable code.
Altera_Forum
Honored Contributor I
65 Views

Thanks for the help guys! I tried running a RTL sim and it worked, so I can move on now. On what Tricky said, none of these entities are meant to be top entities. So I'll stick with ints. Then again I probably should've made a top entity rather than trying to plug three entities directly into a tb

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