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quartus ii internal error!

Altera_Forum
Honored Contributor II
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Hi, 

 

In my quartus project, i add some nodes for debug in SignalTap. While a quartus ii internal error occur when i full compile the design after adding nodes. 

 

The error information is: 

 

Internal Error: Sub-system: HDB, File: /quartus/db/hdb/hdb_grp_inst_sche.cpp, Line: 780 

Bad group type. 

Stack Trace: 

0x3b02d: HDB_INSTANCE_NAME::get_member + 0x11d (DB_HDB) 

0xb5001: HDB_NAME_INFO::~HDB_NAME_INFO + 0xf31 (DB_HDB) 

0x2e007: HDB_NORM_INSTANCE_NAME::get_flag + 0x17 (DB_HDB) 

0x364b9: HDB_INSTANCE_NAME::create_group_helper + 0x1e9 (DB_HDB) 

0x4045f: HDB_INSTANCE_NAME::create_child_helper + 0x52f (DB_HDB) 

0x5580: mem_out_of_memory + 0x4f0 (ccl_mem) 

0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem) 

0x82c5: MEM_SEGMENT_INTERNAL::allocate + 0x95 (ccl_mem) 

End-trace 

Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version 

 

If i disable the "SignalTap II Logic Analyzer", no error occur when compiling! 

 

Has anyone ever met this before?
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Altera_Forum
Honored Contributor II
1,729 Views

You can file a SR to Altera, it looks like a bug. 

I had the same kind of error sometimes when I used an output as a clock in signal tap, try to change a few things in your signaltap setup and see if it gets better.
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Altera_Forum
Honored Contributor II
1,729 Views

 

--- Quote Start ---  

Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version 

--- Quote End ---  

 

 

this is not the latest version, have you installed SP2 ? 

my Quartus 9.1 reports 

 

 

--- Quote Start ---  

Quartus II Version 9.1 Build 350 03/24/2010 SJ Full Version 

Service Pack Installed 2.46 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
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Thanks for your advice. I had tried to add or remove some nodes in SignalTap, and nothing seemed to be better even i keep only one node for debug. The quartus internal error don't occur only if i disable the SignalTap!

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Altera_Forum
Honored Contributor II
1,729 Views

did you try to change the clock used for the signaltap sampling?

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Altera_Forum
Honored Contributor II
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I have tried to change the sampling clock, and error still occurs!

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Altera_Forum
Honored Contributor II
1,729 Views

Hi, MSchmitt and Daixiwen  

 

Thanks for the advice from both of you. After i installed the sp2 for quartus, it seems to be ok now! Maybe it's really a software bug in "Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version".
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Altera_Forum
Honored Contributor II
1,729 Views

I just had one for  

 

Internal Error: Sub-system: HDB, File: /quartus/db/hdb/hdb_inst_name.cpp, Line 696 

 

I was trying to observe one of my PLLs. I went into SignalTap and deleted those signals and it started working again (after much troubleshooting!)
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