Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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quartus24.1 cant generate DP IP

mesile
Beginner
388 Views

Hello, I need help about my quartus24.1 cant generate DP IP, there is an error as shown,

Error:
while executing
"gen_log $temp $log_dir "" "print_warning""
(procedure "gen_qsys" line 25)
invoked from within
"gen_qsys "dp_rx" $tmpdir"
(procedure "generate_qsys_ed" line 181)
invoked from within
"generate_qsys_ed"
(procedure "generate_example" line 10)
invoked from within
"generate_example dp_0_example_design"

 

How can I solve this error?

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ShengN_Intel
Employee
314 Views

Hi,


I think you mean DisplayPort Intel® FPGA IP Core right?

For IP problem, you may open a thread in this forum https://community.intel.com/t5/FPGA-Intellectual-Property/bd-p/fpga-intellectual-property with title target DisplayPort Intel® FPGA IP.


Thanks,

Regards,

Sheng


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