"Access Denied" at the Intel Design Store

[EKuzn5]

I see this writeup among the documentation on the web site:

https://www.intel.com/content/www/us/en/programmable/documentation/rkq1545276609392.html

"AN 883: Intel Arria 10 DisplayPort TX-only Design"

I'd like to pull it and try it out, but the design does not show up in the design store. And the direct link from the writeup

https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/intel-arria-10-displayport-tx-only-design/

gives me a "403: Access Denied" error. (And I can tell that the page does exist, because changing anything in the address turns it into a "404: Page not Found" error.)

Is this a glitch, or do I somehow need special permissions granted to my account to access that link?

[Vicky1]

Hi Eugene, I am also realizing same behavior, it seems to be link broken. let me check internally & get back to you. Regards, Vikas

[sstrell]

It looks like the design is available (filter on Arria 10 devices and search for displayport) but it was not updated for 18.1. You could probably use the 17.0 Pro edition version just fine in 18.0 or even 18.1.

[EKuzn5]

They have two displayport designs available ("DisplayPort UHD Scaler and Mixer Design Example" and "Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Re-transmit Reference Design"), but neither of them is the one I'm asking about. Both of those are retransmit designs, and this one is a TX-only design.

However, I've just noticed that the document describes the process of generating this design manually, I'll attempt that.

[EKuzn5]

Generating it manually is a bit too complicated for my liking (unless I'm missing something). The process is described as follows:

"Instantiate the DisplayPort Intel® FPGA IP ... Click 'Generate Example Design' ... Modify the generated design example by removing the irrelevant blocks from the top-level design and from the dp_core.qsys file.

Remove the RX sub-system, RX PHY top.... instantiate the relevant Video and Image Processing FPGA IPs. ... Connect the CVO II and TPG II Intel® FPGA IP instances ... "

It sounds simple when described like that. The trouble is that there's no top level qsys file. Most of these connections are in the top-level .v file. Therefore, to complete the process, I need to do all these changes (several dozen wires) directly in Verilog.

[JosephC_Intel]

Hi,

We confirmed Internally this issue was fix long time ago. Once you clear your cookies & cache from your browser, thing should be solve.

Thanks,

Joseph