I am working with an Intel Stratix 10 development kit. The model number is DK-DEV-1SGX-L-A. The FPGA type is 1SG280LU2F50EV2G.
The design I am working with is the "AN 829: PCI Express* Avalon® -MM DMA Reference Design."
Originally, I was able to compile the design for the Stratix 10, but it used the H-tile part,
from the DK-DEV-1SGX-H-A development kit, where the FPGA is a 1SG280HU2F50E2VG device. (difference: HU vs. LU in device part number.)
So in Quartus I selected the proper device type. This triggered an auto-update of the IP to be used in building the device. The auto-update seemed to go without error.
However, on recompiling the project, I get the warnings shown in the attached screenshot. And indeed, no bitstream (.sof file) for the device is generated.
I am in over my head on this. I would welcome any advice on how to debug and hopefully correct this problem.
Common Sense Systems, Inc.
For the error, can you please try the solution provided in KDB below ?
let me know if this is helpful.
Hi Wincent -
Thanks for the quick turn around on this. Much appreciated.
I will give your proposed solution a try
Where can I find a pin-out for the FPGA and maybe a schematic for the development board?
I want to make sure I am making the proper connections.
Do you know if the power management connections in the H-tile part (1SG280HU2F50E2VG) would be the same as for the L-tile part, (1SG280LU2F50EV2G)? If the H-tile part is also VID capable, perhaps I could look at the connections that exist for the H-tile part and make them the same for the L-tile part?
Thanks again for any advice you or anyone else can provide.
Common Sense Systems, Inc.
For Stratix 10 Schematic you may get at link below
For Pin-out file please refer
Power manager for H/L tile
Hope this answer your question, let me know if further clarification is needed.
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