"Incomplete power management settings for a VID device"

[JSambrook_CSSI_FPGA]

Hello -

I am working with an Intel Stratix 10 development kit. The model number is DK-DEV-1SGX-L-A. The FPGA type is 1SG280LU2F50EV2G.

The design I am working with is the "AN 829: PCI Express* Avalon® -MM DMA Reference Design."

Originally, I was able to compile the design for the Stratix 10, but it used the H-tile part,

from the DK-DEV-1SGX-H-A development kit, where the FPGA is a 1SG280HU2F50E2VG device. (difference: HU vs. LU in device part number.)

So in Quartus I selected the proper device type. This triggered an auto-update of the IP to be used in building the device. The auto-update seemed to go without error.

However, on recompiling the project, I get the warnings shown in the attached screenshot. And indeed, no bitstream (.sof file) for the device is generated.

I am in over my head on this. I would welcome any advice on how to debug and hopefully correct this problem.

Best Regards,

John Sambrook

Common Sense Systems, Inc.

[wchiah]

Hi John,

For the error, can you please try the solution provided in KDB below ?

https://www.intel.com/content/www/us/en/support/programmable/articles/000086742.html

let me know if this is helpful.

Regards,

Wincent_Intel

[JSambrook_CSSI_FPGA]

Hi Wincent -

Thanks for the quick turn around on this. Much appreciated.

I will give your proposed solution a try

Where can I find a pin-out for the FPGA and maybe a schematic for the development board?

I want to make sure I am making the proper connections.

Do you know if the power management connections in the H-tile part (1SG280HU2F50E2VG) would be the same as for the L-tile part, (1SG280LU2F50EV2G)?  If the H-tile part is also VID capable, perhaps I could look at the connections that exist for the H-tile part and make them the same for the L-tile part?

Thanks again for any advice you or anyone else can provide.

Best,

John Sambrook

Common Sense Systems, Inc.

[wchiah]

Hi,

For Stratix 10 Schematic you may get at link below
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx.html

For Pin-out file please refer

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html

Power manager for H/L tile

https://www.intel.com/content/www/us/en/docs/programmable/683667/21-1/power-management.html

Hope this answer your question, let me know if further clarification is needed.

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel