I want to see paths in my original circuit along with logic element within paths.i write a verilog code, compile it, and then run the time quest timing analyzer in order to check paths and logic element within paths. but timing analyzer optimizes the orignal circuit and generate report paths according to it. e-g in verilog and and RTL view, i have 3 flipflops and 10 gates and time quest optimizes soo much that in post mapping / post fitting i got 3 FlipFlops and 2 gates. and "Report path" show path according to optimize circuit. Is there any way to get "report path" before optimization or without optimization, so that i can get paths in my original circuit. Immediate help in this regard will be appreciated Thankyou for your time and consideration
It's not the timing analyzer that's optimizing your design, it's synthesis and the Fitter. What exactly are you trying to see? The analysis is always based on the netlist or snapshot you choose, so you could try (in the Standard edition) to create the timing netlist based off the post-map netlist (in the Pro edition, you'd select the earliest snapshot available, Planned, I believe). But if your design is already fully compiled, the timing analyzer is always going to use the post-fit netlist in order to provide accurate final timing numbers.
i basically want to generate the report about paths present in a circuit from command "report path" available in timing analyzer but timing analyzer runs after fitter.i m using quartus prime pro edition. my input is verilog code. what i m getting from your response is the timing analyzer is always going to use the post-fit netlist in order to provide accurate final timing numbers. we cannot run timing analyzer before fitter. hence all the results obtain from timing analyzer are based on optimize circuit. m i rite? is there some old version of quartus where we run timing analyzer before fitter. or any other way for locating paths in a circuit. Thankyou for your time and consideration