"derive_pll_clocks" doesn't create generated clocks properly

[SKon1]

"derive_pll_clocks" doesn't create generated clocks properly 

Hello,

In my Arria V design. I have a PLL with one input and 3 outputs. The input is 125 MHz. The outputs are as follows:

1. Output 0 - 125 MHz ( without phase shift - with properties identical to the input clock ).

2. Output 1 - 125 MHz ( without phase shift - with properties identical to the input clock ).

3. Output 2 - 25 MHz.

In Timequest I run "derive_pll_clocks" and look at the output of the command.

I was expecting to see 3 "create_generated_clock" - but I only see one. Only the output for the 3rd clock ( 25 MHz ) has a "create_generated_clock" command.

Why is that ?

[KhaiChein_Y_Intel]

Hi,

Can you share the design for investigation? What is the edition (Pro/Standard) and version you are using?

Thanks.

Best regards,

KhaiY

[SKon1]

The design is attached,

The PLL of interest is named: "pll_ethernet_bridge" and it's located inside an hierarchy named: "ethernet_bridge".

After compiling, I opened Timequest and pressed "derive_pll_clocks".

I looked at the list of generated clocks and it seems like:

1. clock output 0 was created
2. clock output 1 wasn't created
3. clock output 2 was created

I also ran "report_clocks" and looked in the list. The results where the same.

It seems like some kind of optimization is happening in the background.

[SKon1]

Update - I was able to solve it myself using information from this link:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd03062013_146.html

However,

I'm now encountering problems to meet timing.

Please help me with this:

https://forums.intel.com/s/question/0D50P00004eYylhSAC/intel-rgmii-example-output-delay-failure

[KhaiChein_Y_Intel]

Hi,

Sure. We will continue the discussion in the new post.

Thanks.

Best regards,

KhaiY

[SKon1]

As a side note.

IMO, having the fact that Quartus has this option enabled by default is a bad idea.