I am trying to run the simulation model for the readback writeback IP provided by the intel (intel_rdbk_wrbk.ip). Below are the steps I followed for the same:
1. Once HDL for simulation model is generated, I went inside sim/mentor and used "msim_setup.tcl" to create additional do file for running simulation.
2. Let's call this do file "mentor.do". It has some commands to compile the intel IPs for simulation. It also sources msim_setup.tcl file
3. I ran this file using questasim command "vsim -c -do mentor.do".
4. After compiling all development internal IPs, it errors out while compiling the inter_rdbk_wrbk IP.
The error message is:
intel_rdbk_wrbk_191/sim/full_chip/device_params_s10_10m.sv(42): (vlog-13205) syntax error in protected region.
I can see in the Verilog file that this is specifically for the synopsis. I am not sure why mentor specific file is not picked.
I would appreciate any pointers on this.
Let me know if more info is required on this.
Can you point to me the document you are referring to. I have never heard of readback writeback IP in Quartus. If it exists, by default should be there in the IP catalog. Is it a custom IP of yours?
I found "Readback and writeback IP" in this website:
Thanks KY for the information.
How did you add or search intel_rdbk_wrbk ip in Quartus? Is it specifically for a device like DIB IP for S10 10M?