Hi
I want to draw a rectangle(100x100) in the rgb video stream line (640x480) in dsp builder.
So to achieve this, I write code in vhdl and import that file in subsystem builder block in dsp builder. rgb data is not transfering at every clock so I connected valid signal of the data stream line as a clock to vhdl imported file(rectangle).
Data Bus: 8bit.
Valid signal : 1bit
Note: Data Bus and valid signal are separate buses.
But I can not get the required output at the Display(LCD Display).
further I do not know whether I should counter hsync, vsync, front porch, back porch and blanking signals in the data stream line(when the data is in the DSP Builder).
please tell me what mistake I have done here?
I have attached rectangle1.vhd file with this post.
I have also attached the Results of rectangle code along with the code.
Thank You
