second if loop is not working in verilog and latches are generated .how to fix these?

[Altera_Forum]

I'm new to Verilog. I tried the below code calling the 'task' into a if loop.. Syntax is correct. But when I execute behavioral simulation with choice as 010 the loop is not working. The output is shown all zeroes and the synthesis report shows latches are generated..How to fix these two. 

   module a(choice,data1,data2,result);  input[2:0]choice;  input[6:0]data1;  input[8:0]data2;  output[8:0]result;    reg[8:0]reg_result;    wire[3:0]choice;  wire[6:0]data1;  wire[8:0]data2;  wire[8:0]result;    initial///initailllllllllllllllllllllllllll  begin  reg_result=0; //declaring output register to 0 initially  end    always @(data1 or data2 or choice )  begin  if(choice==001)////if loop 1  begin  taskoperation(data1,reg_result);///load result from task   end  if(choice==010)//when choice is given as 010 the simulated output gives me all   begin//zeroes in result(output reg)   taskoperation(data2,reg_result);  end  end  //task operation  task taskoperation(  input [8:0]datainput;  output [8:0]dataoutput  );  dataoutput[8:0]=~(datainput[8:0]);//taskoperation  endtask        assign result=reg_result;    endmodule

[Altera_Forum]

001 and 010 are interpreted as decimal. 'Choice' is 3 bits, it cannot represent decimal 10. If you mean binary, they should be 3'b001, and 3'b010. All 0s are a result of initialization. 

 Other than 001 and 010, there is no default value assigned to reg_result. Thus, synthesis needs to preserve reg_result if 'choice' is not 001 or 010. Therefore results in latches.  If combinatorial logic is what you look for, you can make following changes  always @* // Use '*' to indicate comb logic, synthesis tool will complain if you code wrongly  begin  reg_result = 9'h000; // Or some other default values if 'choice' is not 001 or 010   // Put your old codes here   end  By the way, the 'data1' is 7 bits, not sure it is intentional or typo. A good practice is to keep the arguments passed into task has matching bus width.