set_max_skew timing issue for DDR2 emif on MAX 10

[fpgauser]

Hello,

I have a timing issue on my design using DDR2 controller on max 10 fpga.
In the generated sdc file for the DDR2 controller I have two skew constraints (cf. below):

##################
# #
# READ DATA PATH #
# #
##################

foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
    foreach { dq_pin } $dq_pins {
        set_max_skew -from [get_ports $dq_pin] 0.1
    }
}

#########################
# #
# FALSE PATH #
# #
#########################

foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
    foreach { dq_pin } $dq_pins {
        set_false_path -from [get_registers *dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*] -to [get_ports $dq_pin]
    }
}

set_false_path -rise_from [ get_clocks ${local_pll_write_clk} ] -to [ get_ports $ac_pins ]

foreach { pin } [concat $dqs_pins $dqsn_pins $ck_pins $ckn_pins] {
    set_max_skew -to [get_ports $pin] 0.1
}

At the end of fitting I have no timings errors. But, when I launch TimeQuest and generate all summaries report I have max skew timing violations for both constraints.

I'm using quartus prime standard 16.1 (and I have the same problem with 21.1 version)

Can anyone help me please to fix the problem?

Best regards

[sstrell]

It's difficult without seeing the project or the timing report errors, but I'd guess the I/O locations you've selected are causing the issue.  The Fitter can't meet the requirements to the pins you've selected.  This is MAX 10, so I'm guessing this is a soft controller so it could be placed anywhere in the device.  Check how the Fitter is placing the controller logic.  There may be some other constraints on placement.

[AdzimZM_Intel]

Hello Sir,

Thank you for submitting your question in Intel Community.

I'm Adzim an application engineer will assist you on this thread.

Are you able to provide more details regarding to the timing violation issue?

Is there any simple design that I can use to replicate the issue?

Regards,

Adzim

[fpgauser]

Hello Adzim,

Thank you for you reply.
You can find below (enclosed) screenshots of the timings violations that I have.

For the first violation (related to the 2nd set_max_skew constraint of the SDC), it seems to be normal because, the DQS is generated with pll1|clk[0]_dq_write_clk while, the path violated use pll1|clk[0]_write_clk as launch clock which is 90° phase shiftted. So, the skew constraint of 100ps is unachievable.

The second violation (related to the 1st set_max_skew constraint of the SDC) seems to be only for fitter (overconstraint) and I guess that I should not consider it at the end of my STA analysis.
Could you please confirm my assumptions?


The controller is a soft IP generated by quartus prime software 16.1 and the sdc as well.
The IO locations were defined according to intel recommendations.

Best Regards,

Amine

[AdzimZM_Intel · Accepted solution]

Hi Amine,

I'm agree with your assumption.

Since this is a soft controller, the timing constraint that has been generated may not fix to the design.

I think you can increase the max skew to meet the timing requirement for each port.

Regards,

Adzim

[AdzimZM_Intel]

Hi Amine,

May I know your feedback on my latest reply?

Is there any further question for this thread?

Thanks,

Adzim

[fpgauser]

Hi Adzim,

Thank you for your reply.

Increasing the constraint is not appropriate for our project because, we must do this whenever we regenerate the IP.

So, we decided to keep the violations and add justifications in our design document.

Best regards,

Amine

[AdzimZM_Intel]

Hi Amine,

Thank you for the update. I'm now transition this thread to community support.

If you have a new question, feel free to open a new thread to get support from Intel expert.

Otherwise, the community users will continue to help you on this thread.

Thank you.

Regards,

Adzim