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signal tap logic analyzer trigger hard coded/programmable

AEsqu
Novice
282 Views

signal tap logic analyzer trigger hard coded/programmable

 

Hello,

I used the Xilinx ILA (signal tap with vivado),

there I can change the trigger point and re-grab the data without doing a recompile.

It seems that for Quartus prime std, if the trigger points are changed, you are forced to do a rapid recompile.

Would it be possible in the future to make the trigger point programmable as well for quartus (I use a cyclone 5)?

Or is it possible and I'm missing something?

Alex.

 

 

 

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1 Solution
sstrell
Honored Contributor III
221 Views

It depends on the type of change to a trigger you want to make.  Many simple trigger adjustments (level checking, trigger position, etc.) do not require a recompile.  To see what changes you can safely make without requiring recompilation, set the lock mode just above the Node List in the .stp file.  This will gray out any adjustments that will require recompilation.

Also, by allocating additional node logic resources for tapped signals and triggers (Nodes Allocated options), you can minimize recompile time with Rapid Recompile.  Instead of the Auto option, set the nodes allocated to a greater number.  After a full recompile, you can then add up to that number of tapped nodes with a Rapid Recompile, which is much faster.

This online training was just updated about reducing recompile time:

https://learning.intel.com/developer/learn/course/external/view/elearning/205/signal-tap-logic-analy...

 

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3 Replies
sstrell
Honored Contributor III
222 Views

It depends on the type of change to a trigger you want to make.  Many simple trigger adjustments (level checking, trigger position, etc.) do not require a recompile.  To see what changes you can safely make without requiring recompilation, set the lock mode just above the Node List in the .stp file.  This will gray out any adjustments that will require recompilation.

Also, by allocating additional node logic resources for tapped signals and triggers (Nodes Allocated options), you can minimize recompile time with Rapid Recompile.  Instead of the Auto option, set the nodes allocated to a greater number.  After a full recompile, you can then add up to that number of tapped nodes with a Rapid Recompile, which is much faster.

This online training was just updated about reducing recompile time:

https://learning.intel.com/developer/learn/course/external/view/elearning/205/signal-tap-logic-analy...

 

AEsqu
Novice
197 Views

Thank you for the information, I now select "allow trigger condition changes only".

 

ShengN_Intel
Employee
181 Views

Hi,


Since the issue addressed had been resolved.

I'll now transition this thread to community support.

If you have a new question, feel free to open a new thread to get the support from Intel experts.


Thank you.


Best regards,

Sheng


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