simple Infinite loop expansion header using Altera DE2-70 Cyclon ii

Altera_Forum · ‎04-10-2013

I write a simple infinite loop to generate an output at expansion header. The reason is I want to generate a simple logic digital signal and probe it at MSO oscilloscope, in order to play around with triggering function etc in oscilloscope.

The problem is I got errors:

Error (10106): Verilog HDL Loop error at testing2.v(22): loop must terminate within 5000 iterations Error (12153): Can't elaborate top-level user hierarchy

Is the limit of iterations come from cyclon II or the software? For your information I use free Quartus II 12.1 Web Edition Software.

How to solve it so that I can generate constant (infinite loop) digital signal from expansion header? I also notice that "assign GPIO_0[1] = A;" is not working when we try to use the operational function.

Here is the code. I use the set_global_assignment preference for .qsf file. The .qsf work just fine.

module testing2 (A,B,C,CLOCK_50,GPIO_0,GPIO_1);
output  GPIO_0;
output  GPIO_1;
output  A;
output  B;
output  C;
input CLOCK_50;
reg A, B, C;
assign GPIO_0 = CLOCK_50;
assign GPIO_0 = A;
assign GPIO_0 = B;
assign GPIO_0 = C;
initial 
while(1)
begin
A = 0;
B = 0;
C = 0;# 5
A = 1;
B = 0;
C = 0;# 5
A = 1;
B = 1;
C = 0;# 5
A = 1;
B = 1;
C = 1;# 5
A = 0;
B = 0;
C = 0;
end
endmodule

Thank you for your help!

Altera_Forum · ‎04-10-2013

The limit is there because it cannot convert your code into digital logic. Loops unroll into parrellel logic, and while loops are especially probe to not being synthesisable. So the simple answer is - never use a while loop for synthesisable code. Your code is only suitable as a stimulus for simulation.

Altera_Forum · ‎04-10-2013

Any idea on how to change it from parallel into sequential execution?

If not, do you have any idea or example to generate digital logic pattern signal output at expansion header in DE2-70?

Altera_Forum · ‎04-10-2013

I dont quite understand what you want. The code you have is sequentially executed. It is simulation code. But the synthesisor needs to make a circuit out of it, and loops unroll unto parrallel hardware. Also, timing specs (like the# 5) are completly ignored.

You need to build a system that is synthesisable. Your code suggests you are a software guy. I suggest getting a begineers guide to digital logic, and start reading - forget about the verilog for now.

Altera_Forum · ‎04-10-2013

Sorry I am new to Altera. Previously I was working with PIC and while loop function is working at there. Guess I need to study more on this synthesisable system. Thank you for your reply!

Altera_Forum · ‎04-10-2013

Consider an input clock, a 3-Bit modulo 5 counter clocked by it and a case structure setting the different output patterns based on the counter state.

Altera_Forum · ‎04-17-2013

Dear FvM,

I tried 3-Bit modulo 5 counter as per your suggestion. However, the clock signal is not regenerate smoothly and the flip-flop logic seem different.Herewith I attach the picture of the signals. From bottom; D0 (GPIO_0[0]), D1 (GPIO_0[1]), D2 (GPIO_0[2]), D3 (GPIO_0[3]) and D7 (GPIO_0[7]) at top.

https://www.alteraforum.com/forum/attachment.php?attachmentid=7087

Its generate from .bdf, .v and .sdc

https://www.alteraforum.com/forum/attachment.php?attachmentid=7088

module bitmodulo5( 
    CLOCK_50,     
    GPIO_0,
    VCC
); 
input CLOCK_50; 
input VCC;
output  GPIO_0;
assign GPIO_0 = CLOCK_50;
assign GPIO_0 = VCC;
// Instantiation:
JKFF JKFF_inst
 (.j(GPIO_0), .k(GPIO_0),
   .clk(CLOCK_50), .clrn(GPIO_0), .prn(GPIO_0),
   .q(GPIO_0));
JKFF JKFF_inst1
 (.j(GPIO_0), .k(GPIO_0),
   .clk(CLOCK_50), .clrn(GPIO_0), .prn(GPIO_0),
   .q(GPIO_0));
    
JKFF JKFF_inst2
 (.j(GPIO_0), .k(GPIO_0),
   .clk(CLOCK_50), .clrn(GPIO_0), .prn(GPIO_0),
   .q(GPIO_0));
endmodule

#Constrain the base clock
create_clock -add -period 10.000 
             -waveform { 0.000 5.000 } 
             -name CLOCK_50 
             
# Constrain the divide by 2 register clock
create_generated_clock -add -source CLOCK_50 
             -name div2clock 
             -divide_by 2 
             -master_clock CLOCK_50 
             
                 
create_generated_clock -add -source CLOCK_60 
             -name div2clock 
             -divide_by 2 
             -master_clock CLOCK_50 
             
                 
create_generated_clock -add -source CLOCK_70 
             -name div2clock 
             -divide_by 2 
             -master_clock CLOCK_50 
             
report_ucp -summary

I know there is something wrong with my Clock Constraint. The execution done without error. Which part should I do to generate smooth clock and correct flip-flop logic? Thank you in advance!