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simulate AN812

dsun01
New Contributor III
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Dear Intel support and FPGA expert, 

I am learning Arria 10 dev system. I compiled AN812 and load it successfully to the board. to get better understanding of the DDR4 and EMIF interface. I am creating a simulation environment based on AN812. AN812 was created for Quartus Pro 17. first I need to upgrade to Quartus 21.3. everything compile smoothly, but the top level module, which is top_system. failed to generated testbench. I copied a small section descript the errors.

Info: Starting: Create testbench Platform Designer system
Info: C:/FPGA/an812_orig/complete/top_system_tb/top_system.ipx
Info: qsys-generate C:\FPGA\an812_orig\complete\top_system.qsys --testbench=STANDARD --output-directory=C:\FPGA\an812_orig\complete --family="Arria 10" --part=10AX115S3F45I2SG
Info: Loading complete/top_system.qsys
Info: Reading input file
Info: Parameterizing module cpu_subsystem
Info: Parameterizing module emif_0
Info: Parameterizing module ext_clk
Info: Parameterizing module ext_reset
Info: Parameterizing module memory_tester_subsystem
Info: Building connections
Info: Parameterizing connections
Info: Validating
Info: Done reading input file
Info: qsys-generate succeeded.
Error: Error: Validation of the system failed
Error: There were errors creating the testbench system.
Info: Finished: Create testbench Platform Designer system.

 

What does this error means?  I didn't see it generated any top_system_tb.v or anything like that. 

so, I use Quartus-> processing-> start->start testbench template writer.  created a top_level.vt. 

and use platform designer opened emif_0 qsys.  inside top_system_emif_0_tb, the Platform designer will create a mem_bfm_ip. I guess this is a generic DDR4 behavior model. can I instantiate this module in the AN812 top_level?

 

I did put this module in the top_system.vt, but after some struggle, I can compile and run the simulation. but the behavior is not as expected. I will post the result in another session. 

 

Thank you for all the support, 

David

 

top_system_emif_0_inst_mem_bfm_ip top_system_emif_0_inst_mem_bfm (
.sig_mem_ck (top_system_emif_0_inst_mem_mem_ck), // input, width = 1, conduit.mem_ck
.sig_mem_ck_n (top_system_emif_0_inst_mem_mem_ck_n), // input, width = 1, .mem_ck_n
.sig_mem_a (top_system_emif_0_inst_mem_mem_a), // input, width = 17, .mem_a
.sig_mem_act_n (top_system_emif_0_inst_mem_mem_act_n), // input, width = 1, .mem_act_n
.sig_mem_ba (top_system_emif_0_inst_mem_mem_ba), // input, width = 2, .mem_ba
.sig_mem_bg (top_system_emif_0_inst_mem_mem_bg), // input, width = 1, .mem_bg
.sig_mem_cke (top_system_emif_0_inst_mem_mem_cke), // input, width = 1, .mem_cke
.sig_mem_cs_n (top_system_emif_0_inst_mem_mem_cs_n), // input, width = 1, .mem_cs_n
.sig_mem_odt (top_system_emif_0_inst_mem_mem_odt), // input, width = 1, .mem_odt
.sig_mem_reset_n (top_system_emif_0_inst_mem_mem_reset_n), // input, width = 1, .mem_reset_n
.sig_mem_par (top_system_emif_0_inst_mem_mem_par), // input, width = 1, .mem_par
.sig_mem_alert_n (top_system_emif_0_inst_mem_bfm_conduit_mem_alert_n), // output, width = 1, .mem_alert_n
.sig_mem_dqs (top_system_emif_0_inst_mem_mem_dqs), // inout, width = 4, .mem_dqs
.sig_mem_dqs_n (top_system_emif_0_inst_mem_mem_dqs_n), // inout, width = 4, .mem_dqs_n
.sig_mem_dq (top_system_emif_0_inst_mem_mem_dq), // inout, width = 32, .mem_dq
.sig_mem_dbi_n (top_system_emif_0_inst_mem_mem_dbi_n) // inout, width = 4, .mem_dbi_n
);

 

 

 

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1 Solution
AdzimZM_Intel
Employee
2,276 Views

Hi David,


I think the mem_bfm should be the Intel BFM.

I'm not usually use the AN812 design to test the DDR4 and EMIF interface.

The EMIF IP can generate the example design to simulate and test the IP itself.

You can refer to Arria 10 EMIF Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf


By simulating the example design, you can see all EMIF signals interaction from the memory initialization ,calibration flow and user accesses.

I'm not sure if this something that you trying to get but I'm sure this can give you a good understanding on how the DDR4 and EMIF interface simply work.


Thanks,

Adzim


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7 Replies
AdzimZM_Intel
Employee
2,277 Views

Hi David,


I think the mem_bfm should be the Intel BFM.

I'm not usually use the AN812 design to test the DDR4 and EMIF interface.

The EMIF IP can generate the example design to simulate and test the IP itself.

You can refer to Arria 10 EMIF Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf


By simulating the example design, you can see all EMIF signals interaction from the memory initialization ,calibration flow and user accesses.

I'm not sure if this something that you trying to get but I'm sure this can give you a good understanding on how the DDR4 and EMIF interface simply work.


Thanks,

Adzim


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dsun01
New Contributor III
2,268 Views

Hi Adzim

 

Thank you for your prompt response, really appreciate your help. 

I will read the document and give it a try.

 

David

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dsun01
New Contributor III
2,264 Views

Hi Adzim

 

I may be happy too early.  the document is good, but in Quartus 21.3, to follow it step by step doesn't work.  I guess there is a very minor variation between the tools revisions. 

 

here are the error message.  I got this error message, could you please have a look and give me some suggestion, I guess just one step away from it. 

Thank you

 

Error: (vsim-8345) Unable to find original top-level design units for optimized design "_opt".

 

# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2958) Implicit wire '<protected>' does not have any driver.
# ** Warning: C:/FPGA/EMIF_SIM/emif_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr4_191/sim/altera_emif_ddrx_model_rank.sv(1196): (vopt-2697) MSB 19 of part-select into 'address' is out of bounds.
# ** Error: (vsim-8345) Unable to find original top-level design units for optimized design "_opt".
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=333.
# Error loading design
# End time: 08:36:23 on Feb 17,2022, Elapsed time: 0:00:28
# Errors: 1, Warnings: 333

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dsun01
New Contributor III
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Hi Adzim

 

Sorry, I should use Questa-Intel. now it is running. and I got the waveform looks very reasonable. but the transcript windows dump a lot of information like this.

 

why it kept warning.  is there a parameter can turn it off, if it now important. 

READ Warning: IOAux detected dirty input data.

 

----------------------------------------

 

[2238863560] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: Initiating Read operation from [0x9aab]
# [2238863560] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: READ Warning: IOAux detected dirty input data.
# It is possible that your read operation may contain invalid data.
# [2239014600] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: READ: [0x9aab] => 0x0000000a ( 31 cycles)
# [2241129160] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfc420] <= 0x00000000
# [2241280200] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfc421] <= 0x00001f00
# [2241431240] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfc4a0] <= 0x00000000
# [2241582280] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfc4a1] <= 0x00001f00
# [2241733320] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfc380] <= 0x00000000
# [2242035400] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x6080] <= 0x00000008
# [2242186440] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: Initiating Read operation from [0x60c0]
# [2242255860] [DWR=000]: PRECHARGE - C [ 0 ] - ALL BANKS
# [2242337480] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: READ: [0x60c0] => 0x00000013 ( 31 cycles)
# [2242790600] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x6080] <= 0x00000008
# [2242941640] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: Initiating Read operation from [0x60c0]
# [2243011060] [DWR=000]: PRECHARGE - C [ 0 ] - ALL BANKS
# [2243092680] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: READ: [0x60c0] => 0x00000013 ( 31 cycles)
# [2245056200] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x5240] <= 0xffff0000
# [2245509320] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x5280] <= 0x00000000
# [2246113480] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x52c0] <= 0xffff0000
# [2246566600] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4000] <= 0x00000000
# [2247170760] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4800] <= 0x00000000
# [2247623880] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4840] <= 0x00000000
# [2248228040] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4880] <= 0x00000000
# [2248832200] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x48c0] <= 0x00000000
# [2249436360] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4900] <= 0x00000000
# [2250040520] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4940] <= 0xffff0000
# [2250644680] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4980] <= 0x00000000
# [2251097800] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x49c0] <= 0x00000000
# [2251701960] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4a00] <= 0x00000000
# [2252306120] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4a40] <= 0x00000000
# [2252910280] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4a80] <= 0xffff0000
# [2253363400] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x4ac0] <= 0x00000000
# [2253967560] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x50c0] <= 0xffff0000
# [2254571720] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x5100] <= 0x00000000
# [2255024840] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0x51c0] <= 0x00000f0f
# [2255326920] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfe091] <= 0x01000020
# [2255477960] IOAux instance ed_sim.emif_0.emif_0.arch.arch_inst.io_aux_inst.io_aux.inst.<protected>.<protected>: WRITE: [0xfe090] <= 0x7c7f0001

 

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AdzimZM_Intel
Employee
2,244 Views

Hi David,


I think that are part of the transaction process of the DDR operation.

As you can see that they are trying to perform the read and write operation at the moment.


I don't think you can turn off or hide this particular message/warning.

It's should be contained an important info whenever the memory performs the wrong transaction.

But I think your design is doing good and maybe you can ignore that message.


Thanks,

Adzim


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dsun01
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AdzimZM_Intel
Employee
2,226 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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