Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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simulation doesn't work well

Altera_Forum
Honored Contributor II
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hi, i asked to build a multiplier 2X4. 

my problem, as you can see in the image, that signal s5 starts one cycle before the others. 

all the signals connected well and i have no idea why it happend. 

i have checked my mul and it works well. 

you can see my code and the simulation at the links below. 

thanks
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Altera_Forum
Honored Contributor II
607 Views

Hi, 

 

Just wonder if it is possible for you to initialize the output value ie to 0 to ensure the output to have same values at the beginning of the simulation.
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Altera_Forum
Honored Contributor II
607 Views

Its definitely a signal initialisation issue. You need to ensure the values in your testbench that drive your DUT are given initial values.

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Altera_Forum
Honored Contributor II
607 Views

do you mean that i need to initialize the register? 

reser = '0' ? 

or initialize the output of the component? and then how i do it?
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Altera_Forum
Honored Contributor II
607 Views

Usually you can define signal name : type := default_value.

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Altera_Forum
Honored Contributor II
607 Views

thank you 

works well
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