simulation problems:Warning: (vsim-3473) Component instance "i1 : ex1" is not bound.

[Altera_Forum]

hi everyone: 

i build a simple project, use schematic as top, when i want to simulate the project, the modelsim shows: Warning: (vsim-3473) Component instance "i1 : ex1" is not bound. Time: 0 ps Iteration: 0 Instance: /ex1_vhd_tst File: E:/SF_CY3/QD_SF_CY3/EX1/simulation/modelsim/ex1.vht   it looks like the modelsim did not recognize the component in the schematic, why this happens and how to fix it?  thanks!

[Altera_Forum]

Modelsim needs to compile all the components in your design. This message means that you have not told Modelsim to compile the component ex1. 

 Your filename looks a little weird, is ex1.vht supposed to be your testbench file? A more normal convention would be the component source is ex1.vhd and the testbench source is ex1_tb.vhd.   But since you said that your top-level design was a schematic, perhaps that it just what Quartus generates. In that case, you may have a problem with your top-level design being called ex1, and your component being called ex1. If that is the case, change your schematic name to ex1_top.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Modelsim needs to compile all the components in your design. This message means that you have not told Modelsim to compile the component ex1.  Your filename looks a little weird, is ex1.vht supposed to be your testbench file? A more normal convention would be the component source is ex1.vhd and the testbench source is ex1_tb.vhd.   But since you said that your top-level design was a schematic, perhaps that it just what Quartus generates. In that case, you may have a problem with your top-level design being called ex1, and your component being called ex1. If that is the case, change your schematic name to ex1_top.  Cheers, Dave  --- Quote End ---    thanks for the help! i am new guy to altera, maybe i am not familiar to the quartus tools, but i feel the simulation of the quartus is not as friendly as ise. how can i do if i want to sim one of the vhd file of the project?  is there any manual or handbook for new ones to study how to simu a project? thanks!

[Altera_Forum]

actually the test bench is *.vht(*.vt for verilog) even if i use vhd(or verilog) as top, the way i generate the test bench is processing=>start=>start test bench template writer 

 if find a way to fix the problem: let the quartus generate a vhd file for the sch, then delete the sch file, make the vhd file as the top, then simulate...

[Altera_Forum]

--- Quote Start ---   i am new guy to altera, maybe i am not familiar to the quartus tools, but i feel the simulation of the quartus is not as friendly as ise. how can i do if i want to sim one of the vhd file of the project?  is there any manual or handbook for new ones to study how to simu a project? thanks!  --- Quote End ---    Quartus and Modelsim are totally separate tools from separate vendors. Personally I never run Modelsim from Quartus, and I never have Quartus generate a testbench.  My recommendation for development is to write everything in a hardware description language, eg., VHDL or SystemVerilog (of which Verilog is a subset). Modelsim can be used to simulate that code independent of Quartus. Once your simulation operates correctly, then you can synthesize the top-level design.  Things get a little trickier with Qsys systems, since you have to use Quartus to generate the Qsys system code, and then once you have that you can simulate with Modelsim.  I've posted some simple Modelsim simulations;  http://www.alteraforum.com/forum/showthread.php?t=45770 http://www.alteraforum.com/forum/showthread.php?t=32386  Try those and you'll see how the code and testbench can be structured.  Cheers, Dave