smart triggering in Quartus' s signal tap

[Altera_Forum]

Hello everyone, 

I'm trying to detect and correct a possible bug in my firmware, and in order to do this I should set up the ST's trigger in a smart way. I have this two signals (basically a token-in and a token-out between the FPGA and a time-to-digital converter) which at some point, after the state machine is turned on, become inverted, i.e. the token-out happens before the token-in. This obviously causes problems when data are sent. In order to understand the problem, I would need to trigger exactly when the first of these inverted events takes place, so that I can look at the other signals in my ST and see which one behaves badly (the cause can be manyfold, so I added several signals in the ST). What I'd like to do is to trigger "IF this signal (token-in) is up AND after n clock cycles this other signals(token-out) is up". The inverted case must obviously be excluded, otherwise the ST will trigger on regular events, happening as I turn the state machine on. Can anyone tell me how can I obtain such a trigger in the ST's trigger manu (if it is possible)? Thank you! Regards   Stefano

[Altera_Forum]

I don't quite get your point but in many such cases I added a small state machine for triggering. You can detect internally the pattern that you want to capture and pass it to a single signal or value from the state machine including a manual reset input to repeat the process.

[Altera_Forum]

I think state-based triggering (http://www.altera.com/support/examples/on-chip-debugging/signal-tap/signaltap2-design-examples.html?gsa_pos=3&wt.oss_r=1&wt.oss=signaltap%20state) is what you looking for.

[Altera_Forum]

if you need something more complicated, its usually easiest just to stick some logic in your source code and use a basic trigger to see when an event occurs. Tie this in with the "noprune" attribute and you can connect signal tap to dangling logic.