specifying false paths

[Altera_Forum]

Hi All, 

 I'm a bit confused on specifying false paths and the use of -to, -through, and -from. For -to and -from, do these have to be the source (q) and end (d) of some datapath? Or can they be combinational signals along the way? TimeQuest won't let me specify two -through arguments, so can i use a -from and a -through if neither of these are the source of the data in the timing path?  Also, I've been referring to the SDC and TimeQuest API Reference Manual, and they're is a notion of cells, clocks, nets, pins, ports, fanins, fanouts, keepers, nodes, partitions and registers. Some of the commands, like false path, specify what you can use with which argument. But I don't think I know what all of these are. Can someone add / correct my list?  cell: ? clocks: anything you declare as a clock with create_clock or create_generated_clock pins: connections of any verilog module? ports: connections to the top level module, usually connect to physical pins? fanins: ? fanouts: ? keepers: registers and ? nodes: ? partitions: ? registers: outputs of ff  Thanks a lot,  Steve

[Altera_Forum]

Go to View -> Name Finder in TimeQuest and you can play with these. 

Cell is a physical thing in the device, like a LUT, FF, PLL, memory slice, etc. Pin is the connection on these cells, so it doesn't relate directly to your hdl. A FF will have pins like |clk, |d, |q. A LUT will usually have |combout. Keepers are timing endpoints. Mainly FFs and Ports. RAMs you can write to asynchronously(old LUTRAMs) could be them. Registers are just a subset of the keepers. Personally, I use keepers for my -from/-to options if I want a specific path, and clocks if I want to modify a whole domain. The only time I use -pin is with the -through option, such as going through a particular LUT, or to make generated clock assignments on gated clocks(such as the |combout of the mux done in logic). I use ports for I/O constraints. The -from and -to must be endpoints of the path of clock domains. I almost exclusively use those, and often only one(in which case the other defaults to "everything"). I very seldom use -through except occasionally in report_timing. I've never seen the need for two options for -through, so you may have a unique case. Doesn't answer everything but hope it helps.

[Altera_Forum]

--- Quote Start ---  Hi All,  I'm a bit confused on specifying false paths and the use of -to, -through, and -from. For -to and -from, do these have to be the source (q) and end (d) of some datapath? Or can they be combinational signals along the way? TimeQuest won't let me specify two -through arguments, so can i use a -from and a -through if neither of these are the source of the data in the timing path?  Also, I've been referring to the SDC and TimeQuest API Reference Manual, and they're is a notion of cells, clocks, nets, pins, ports, fanins, fanouts, keepers, nodes, partitions and registers. Some of the commands, like false path, specify what you can use with which argument. But I don't think I know what all of these are. Can someone add / correct my list?  cell: ? clocks: anything you declare as a clock with create_clock or create_generated_clock pins: connections of any verilog module? ports: connections to the top level module, usually connect to physical pins? fanins: ? fanouts: ? keepers: registers and ? nodes: ? partitions: ? registers: outputs of ff  Thanks a lot,  Steve  --- Quote End ---    Adding my thoughts to Rysc notes:  The term "register" is used synonymous as FF by most of us (not as Uni definition) because FPGA engineers don't seem to like FF letters! clock: any signal that is connected to clock port of a register be it proper clock or accidental gating by newbies. fanin in the context of timing refers(I believe) to signals entering a cloud of logic that eventually feeds D input of a register. fanout in same context refers to signals leaving Q output of a register or clouds to various clouds around. node : any point with unique drive or logic value. e.g. five signals wired together is one node no matter what names we use for them at declaration.  Imagine rtl as the triad unit of [launch register => combinatorial cloud => latch register] as simplest case then add to it guest signals coming from other such units around which could be direct from other registers or from within their clouds. Reset has high fanout entering many registers directly or a certain control signal fanning out to many layers of rtl leading to long paths and timing problems.  The simplest path is reg => reg with zero cloud. Next come paths with single isolated cloud e.g. C <= A+B assuming A,B,C are registers and addition is unconditional. A fanin occurs if you add condition on adder operation from a signal originating somewhere else. An unconditional accumulator running say 0~15 is a special case of launch/latch being same register.  Thus paths may not be simple reg => cloud => reg path. TimeQuest allows you to control this tree of a path fanin/fanout as explained by Rysc using the switches -to, -from, -thru, and also -start, -end ...

[Altera_Forum]

That's helpful, thanks folks.