This is partly from a previous thread "converted to equivalent circuits with latches". As shown below:always @(posedge clk or posedge reset) begin if(reset) begin: OVER_LOOP // totally 8 loops for one group of calculation ... ; end else if (clk) begin ... ; end // end of if OVER_LOOP end // end of always If I use synchronous bit loading, the latches are all gone. However, since I have to use if...else structure instead if...if, the first round of data calculation loop has to start at the rising edge of 10th clock with the 9th clock period being used for reset and initialization. Is there a design that I could use the falling edge of clock for reset and initialization so that the rising edge of 9th clock can be used for the new round of data calculation? In this way, the design can be faster by 1/9. Or, if the reset signal has to be released at the rising edge of clock signal, there simply no way to speed up the design in this way?
Again, is there a way I could do the reset for the initial values, and at the same time, do the calculation for the next round of 8 iterations in one clock cycle? I try to put if...if there, so that the two if blocks could be done sequentially in one clock cycle, but Verilog doesn't allow me to do so.Thanks for any ideas to solve the problem in advance!