state of FPGA pins before bitmap takes effect

[Altera_Forum]

Hi All, 

 There is a short interval between the time I powered up my FPGA board and the time my bitmap takes effect.   Is there a way to define/ control the logic high/low state of FPGA output pins in this time interval? I mean, to define/ control from FPGA chip itself, not from other components on the board.  Thanks.

[Altera_Forum]

--- Quote Start ---   Is there a way to define/ control the logic high/low state of FPGA output pins in this time interval? I mean, to define/ control from FPGA chip itself, not from other components on the board.   --- Quote End ---   It depends on the FPGA.  Some FPGAs have an IO_PULLUP pin that can be used to define whether weak pull-ups are enabled or not during power on, i.e., you have a "global" option, rather than a per pin option.  Generally I use pull-up or pull-down resistors on control signals that I want to guarantee have a particular state when the FPGA is not configured.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  It depends on the FPGA.  Some FPGAs have an IO_PULLUP pin that can be used to define whether weak pull-ups are enabled or not during power on, i.e., you have a "global" option, rather than a per pin option.  Generally I use pull-up or pull-down resistors on control signals that I want to guarantee have a particular state when the FPGA is not configured.  Cheers, Dave  --- Quote End ---    Hi Dave,  Thanks for the reply. I am using Cyclone IV FPGA. Does it have the IO_PULLUP pin you mentioned? Also, how I control this IO_PULLUP pin?

[Altera_Forum]

I look at Cyclone IV device manual.  

 http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf  It says this:  I/O Pins Remain Tri-stated During Power-Up The output buffers of Cyclone IV devices are turned off during system power up or  power down. Cyclone IV devices do not drive out until the device is configured and  working in recommended operating conditions. The I/O pins are tri-stated until the  device enters user mode.  So I would conclude that we cannot define/ control the logic high/low state of FPGA output pins before bitmap takes effect.  Comments/ corrections are welcome.

[Altera_Forum]

--- Quote Start ---  I am using Cyclone IV FPGA. Does it have the IO_PULLUP pin you mentioned? Also, how I control this IO_PULLUP pin?  --- Quote End ---    The Cyclone IV does not appear to have an IO_PULLUP control (the Stratix II has that pin).  A search of pull-up in the Cyclone IV handbook yields the following statements:  "The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after POR) before and during configuration."  and then a little later on  "In user mode, the user I/O pins function as assigned in your design and no longer have weak pull-up resistors."  So, the FPGA has weak pull-ups enabled when the device is not configured. If you want an external signal held low, then you'll have to use a pull-down.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  It depends on the FPGA.  --- Quote End ---   All Cyclone devices have a weak pull-up after power-on and during configuration. Value between 7k and 352k depending on IO voltage and PVT (Process, Voltage, Temperature). See page 457 (Volume 3 page 1-11 Table 1-12) of the Cyclone IV Handbook    --- Quote Start ---  Some FPGAs have an IO_PULLUP pin that can be used to define whether weak pull-ups are enabled or not during power on, i.e., you have a "global" option, rather than a per pin option.  --- Quote End ---   I don't recall Cyclone devices to have this feature.    --- Quote Start ---  Generally I use pull-up or pull-down resistors on control signals that I want to guarantee have a particular state when the FPGA is not configured.  --- Quote End ---   Usually you would only need external pull-down resistors, but they may have to be as low as 1k, external pull-up resistors can be any value.