synthesis - entity with multiple architectures

[Altera_Forum]

Hello there, 

I have a little problem synthesizing a vhdl design  which has 2 architectures for the same entity (I use Quartus II 13.0.0). I have 2 files for the 2 architectures of the entity, each file having the same entity declaration at the start of file. With my modelsim simulation everything runs fine:  I have put a configuration to the top level and with that I can select the architecture in use:  ****************** File: SumAbsDifference_Arch00.vhd ... ENTITY hk_SumAbsDifference is PORT (  --control signals clr_n : IN STD_LOGIC; clk : IN STD_LOGIC; ... );  ARCHITECTURE arch0 OF hk_SumAbsDifference IS signal referenceDataArray : hk_TemplateArray; BEGIN ... END arch0;  ****************** File: SumAbsDifference_Arch01.vhd ... ENTITY hk_SumAbsDifference is PORT (  --control signals clr_n : IN STD_LOGIC; clk : IN STD_LOGIC; ... );  ARCHITECTURE arch1 OF hk_SumAbsDifference IS signal referenceDataArray : hk_TemplateArray; BEGIN ... END arch1;   ****************** toplevel.vhd ... configuration cfg_TB1 of hk_SingleTemplateMatching is  for arch1  for SumAbsDifference_tb : hk_SumAbsDifference   use entity work.hk_SumAbsDifference(arch0);  -- use entity work.hk_SumAbsDifference(arch1);  end for; end for; end;  ****************** However the QII synthesis produces a  Error (10430): VHDL Primary Unit Declaration error at SumAbsDifference_Arch01.vhd(30): primary unit "hk_SumAbsDifference" already exists in library "work" which I think is due to the 2 identical entity declarations in the two files (however with different architecture name)   Well of course there are several ways to patch the problem e.g. by using two different entity names or by only selecting SumAbsDifference_Arch01.vhd in the project's file list. But is there a clean (best practice) way for doing this by configuration ?  Thanks and kind regards !

[Altera_Forum]

Quartus expects one unique entity definition that may have multiple architectures. Without configuration it uses the last one, if I remember right.

[Altera_Forum]

You can have multiple architectures in a single entity, but you must have a SINGLE entity. 

Merging the two SumAbsDifference_Archxx.vhd files and using a single ENTITY declaration I think should work.

[Altera_Forum]

I solved the problem. 

I put the entity to an extra file: ****************** File: SumAbsDifference_Entity.vhd  ENTITY hk_SumAbsDifference is PORT (  clr_n : IN STD_LOGIC; clk : IN STD_LOGIC; ... );  END hk_SumAbsDifference; ******************  and the two architectures (without entity ) in the two files  ****************** File: SumAbsDifference_Arch00.vhd  ARCHITECTURE arch0 OF hk_SumAbsDifference IS signal referenceDataArray : hk_TemplateArray; BEGIN ... END arch0;  ****************** File: SumAbsDifference_Arch01.vhd  ARCHITECTURE arch1 OF hk_SumAbsDifference IS signal referenceDataArray : hk_TemplateArray; BEGIN ... END arch1; ******************  The configuration I had to put into the .vhd where the component is instantiated.  ****************** File: SingleTemplateMatching.vhd  configuration cfg_TB1 of hk_SingleTemplateMatching is  for ar1 for SumAbsDifference_tb : hk_SumAbsDifference  -- use entity work.hk_SumAbsDifference(arch0); -- general n-Bit version NOT optimized  use entity work.hk_SumAbsDifference(arch1); -- non lossy version 15 bit  end for; end for; end;  ****************** otherwise I would have to stepwise go through all the submodules (TL->Nios->DMAComponent->HWTop->...) and create configurations  which one calls the other  (like in: http://www.altera.com/support/kdb/solutions/rd07032012_70.html ) Thanks for your quick responses (the basic idea was, that a second entity definition is forbidden even if it is identical to the first).  Kind regards