In Quartus, is synchronous processes allowed in system verilog interfaces for synth? I'm seeing messages from quartus indicating that logic signals need an initial value, even when they are assigned as a wire to values that are generated within the interface.
Warning (10030): Net "if_my.signal" has no driver or initial value, using a default initial value '0'
Code in interface:
assign signal = local_generated_signal && logic_interface_signal;
You may need to refer to below link for details. I believe system verilog also work as verilog where you need to manually assign value to the net.