test bench

[Altera_Forum]

Hi every one  

i full the test bench code inside the test bench format template that i got it during compilation .Problem with clock time , I have not seen any sign of changing times, There are also a problem in the Q and cout. as shown in wave pic. I am grateful for any help or advice from any friend so that I could examine the theis test bench, thanks for all.

[Altera_Forum]

You must change your two processes: 

  

• Make a process for the clock: 

  Clock_Process: PROCESS BEGIN clock <= '0'; WAIT FOR 50 ns; clock <= '1'; WAIT FOR 50 ns; -- Do not put 'WAIT;' as it will force the process -- to wait forever and consequently, clock will never toggle. END PROCESS; 

• Make a process for the reset: 

  Reset_Process: PROCESS BEGIN Resetn <= '0'; -- Active low reset WAIT FOR 201 ns; -- Maintain low reset during 201ns Resetn <= '1'; -- Release resetn WAIT; END PROCESS; 

• Make a process for the input data: 

 always : PROCESS -- optional sensitivity list ( clock ) BEGIN -- code executes for every event on sensitivity list carry_in <= '0'; -- First carry_in value (input of your block) D <= "1101"; -- First D value (input of your block) wait for 300ns; wait until rising_edge(clock); -- wait until rising edge of clock wait for 1ns; -- Just to model the Tco of flip-flop carry_in <= '0'; -- Second carry_in value (input of your block) D <= "1101"; -- SecondD value (input of your block) wait; -- You can use this as this is the last data of your test bench END PROCESS always;

[Altera_Forum]

Thank you very much( mr.adouville) for the code you sent to me, The program did not work (when i cheeked by run analysis &elaboration process's) because of the WAIT state( may be it must to change the type of file for another HDL file . Please if you can to help mi or give any advice to resolve this problem

[Altera_Forum]

you cant have wait statements f you have a sensitivity list. delete the sensitivity list on a process with wait statements in.

[Altera_Forum]

Hi thanks for advice, but when i delete the sensitivity list then i cant processed the code, i try this way.,but no progress

[Altera_Forum]

--- Quote Start ---  Hi thanks for advice, but when i delete the sensitivity list then i cant processed the code, i try this way.,but no progress  --- Quote End ---   You should consider being more specific about what you mean...it's totally unclear about where you're having problems. Below is some code (untested, not even compiled, up to you to fix) that will generate the stimulus to test your widget    LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; ENTITY Block4CLA_vhd_tst IS END Block4CLA_vhd_tst; ARCHITECTURE Block4CLA_arch OF Block4CLA_vhd_tst IS -- constants constant CLOCK_PERIOD: time := 100 ns; -- signals SIGNAL carry_in : STD_LOGIC; SIGNAL clock : STD_LOGIC := '0'; SIGNAL Cout : STD_LOGIC; SIGNAL D : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL Resetn : STD_LOGIC; signal Sim_Complete: std_logic := '0'; BEGIN i1 : entity work.Block4CLA PORT MAP ( -- list connections between master ports and signals carry_in => carry_in, clock => clock, Cout => Cout, D => D, Q => Q, Resetn => Resetn ); clock <- not(clock) and not(Sim_Complete) after (CLOCK_PERIOD / 2); Resetn <= '0', '1' after 201 ns; Main : process begin d <= "0000"; carry_in <= '0'; wait until (Resetn = '1') and rising_edge(Clock); for c in 0 to 1 loop if (c = 0) then carry_in <= '0'; else carry_in <= '1'; end if; for d_loop in 0 to 15 loop d <= std_logic_vector(to_unsigned(d_loop, d'length)); wait until rising_edge(clock); -- Add assertions here to check that the outputs Q and Cout are correct end loop; end loop; Sim_Complete <= '1'; wait; end process Main; END Block4CLA_arch;  Kevin Jennings

[Altera_Forum]

Hello sir 

I have aproblem when i tested (the both two codes)by run analysis &elaboration process's i recieved : ( Process Statement must contain only one Wait Statement) ,also i modified the code but with each run i got same of errors about the WAIT statement. How can to test the design whith out using the WAIT case inside the code?

[Altera_Forum]

--- Quote Start ---    Hello sir I have aproblem when i tested (the both two codes)   --- Quote End ---   Are we supposed to guess correctly about what 'both two codes' is supposed to be referring to?   --- Quote Start ---  by run analysis &elaboration process's i recieved : ( Process Statement must contain only one Wait Statement) ,also i modified the code but with each run i got same of errors about the WAIT statement.   --- Quote End ---   Since it is totally unclear what code you're talking about but this thread is about your testbench, then I'm guessing that you're trying to compile the testbench in Quartus...that won't work. Quartus is used to synthesize logic and produce bitstream that can be loaded into a device which then implements the logic that was described.   A testbench on the other hand is NOT supposed to be synthesized, it is not to be implemented at all, therefore you would not use Quartus with such code. A testbench is a model of the system in which your design will ultimately live. It is meant to be interpreted by a simulator (like Modelsim, Aldec, GHDL).   --- Quote Start ---  How can to test the design whith out using the WAIT case inside the code?  --- Quote End ---   See above...you use a simulator with your testbench and your design...not Quartus. But again, I'm just guessing since you're not referencing just what code it is you're getting the error.   Kevin Jennings

[Altera_Forum]

Hello sir 

i mean the code that you sent it and the first one in which i received before (on my page) .I want to used this code to test the design inside Quartusii (and because that i must run the analysis & elaboration process's) with test bench format template that i got from quatrus ii which Supplied in the below. I hope that I have explained my request

[Altera_Forum]

you cannot compile this code in quartus. For a start, you have no inputs or outputs, so Quartus will simply compile it all away to nothing. And secondly - quartus is NOT a application designed for testing. You need to use something like modelsim.

[Altera_Forum]

Hello  

automatic (functional and timing )simulation can be finshed inside quartus ii by setting the design to run in quartus and use EDA tool for simulation, and this should be used the test bench code for the project and start elabobation procces before running the eda simulation tool

[Altera_Forum]

--- Quote Start ---  Hello  automatic (functional and timing )simulation can be finshed inside quartus ii by setting the design to run in quartus and use EDA tool for simulation, and this should be used the test bench code for the project and start elabobation procces before running the eda simulation tool  --- Quote End ---   To repeat...Quartus is not a simulation tool, it is a synthesis tool. The setting that I think you are referring to in Quartus for EDA tool for simulation does not run a simulation, what it does is tell Quartus which tool you are using for simulation.   Quartus can then be setup to automatically run the simulation if you want, but this is not required. You can simply open the simulator, compile the source files and run the simulation without involving Quartus at all.   The problem you seem to be having with not being able to analyze and elaborate the design in Quartus is caused by one of two things: - You have syntax problems in your design - You are including the testbench file into your Quartus project.   Assuming that the problem is the testbench has been included into your Quartus project you have two solutions: - Remove the testbench file into your Quartus project. - Add pragmas at the start and end of the architecture as indicated below    ARCHITECTURE Block4CLA_arch OF Block4CLA_vhd_tst IS ... begin --synthesis translate_off ... All of the current architecture stuff that you have would go here. The translate_off/on pragmas tell Quartus to ignore whatever is in between. --synthesis translate_on ... END Block4CLA_arch;    Kevin Jennings