testbench

Altera_Forum · ‎10-09-2012

I wonder what is wrong when i drive modelsim...

here is the testbench code. :confused:

-- Generated on "10/05/2012 12:26:11"

-- Vhdl Test Bench template for design : uppgift_3b

--

-- Simulation tool : ModelSim-Altera (VHDL)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY uppgift_3b_vhd_tst IS

END uppgift_3b_vhd_tst;

ARCHITECTURE uppgift_3b_arch OF uppgift_3b_vhd_tst IS

-- constants

-- signals

SIGNAL addr_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL addr_rom : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL clk : STD_LOGIC:='0';

SIGNAL data_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL q_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL q_rom : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL we_ram : STD_LOGIC;

COMPONENT uppgift_3b

PORT (

addr_ram : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

addr_rom : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

clk : IN STD_LOGIC;

data_ram : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

q_ram : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

q_rom : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

we_ram : IN STD_LOGIC

);

END COMPONENT;

BEGIN

i1 : uppgift_3b

PORT MAP (

-- list connections between master ports and signals

addr_ram => addr_ram,

addr_rom => addr_rom,

clk => clk,

data_ram => data_ram,

q_ram => q_ram,

q_rom => q_rom,

we_ram => we_ram

);

clk<= not(clk) after 20 ns;

init : PROCESS

-- variable declarations

BEGIN

WAIT FOR 100ns;

addr_ram <= "01";

WAIT FOR 100ns;

addr_rom <= "10";

WAIT FOR 100ns;

data_ram <= "011";

WAIT FOR 100ns;

we_ram <= "1";

-- code that executes only once

WAIT;

END PROCESS init;

END uppgift_3b_arch;

Altera_Forum · ‎10-09-2012

what errors do you get?

Altera_Forum · ‎10-09-2012

# Reading C:/altera/12.0/modelsim_ase/tcl/vsim/pref.tcl # do uppgift_3b_run_msim_rtl_vhdl.do # if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Copying c:\altera\12.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied c:\altera\12.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vcom -93 -work work {C:/altera_trn/VHDL_kurs/uppgift_3b/uppgift_3b.vhd}# Model Technology ModelSim ALTERA vcom 10.0d Compiler 2012.01 Jan 18 2012# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package NUMERIC_STD# -- Loading package std_logic_arith# -- Loading package STD_LOGIC_UNSIGNED# -- Compiling entity uppgift_3b# -- Compiling architecture BLOCK_RAM_ROM_FPGA of uppgift_3b# # vcom -93 -work work {C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht}# Model Technology ModelSim ALTERA vcom 10.0d Compiler 2012.01 Jan 18 2012# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity uppgift_3b_vhd_tst# -- Compiling architecture uppgift_3b_arch of uppgift_3b_vhd_tst# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(72): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(74): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(76): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(78): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(79): String literal found where non-array type ieee.std_logic_1164.STD_LOGIC was expected.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(73): (vcom-1272) Length of expected is 3; length of actual is 2.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(85): VHDL Compiler exiting# ** Error: c:/altera/12.0/modelsim_ase/win32aloem/vcom failed.# Error in macro ./uppgift_3b_run_msim_rtl_vhdl.do line 10# c:/altera/12.0/modelsim_ase/win32aloem/vcom failed.# while executing# "vcom -93 -work work {C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht}"#

these ....?

Altera_Forum · ‎10-09-2012

--- Quote Start ---

String literal found where non-array type ieee.std_logic_1164.STD_LOGIC was expected.

--- Quote End ---

we_ram <= "1";

When you use double quotes, it declares a vector, even if you have one bit. So "1" is a 1-bit std_logic_vector, not a std_logic. Try using '1' instead, which will be a std_logic.

--- Quote Start ---

(vcom-1272) Length of expected is 3; length of actual is 2.

--- Quote End ---

addr_ram <= "01";

As the message says, addr_ram is a 3 bit vector and you are trying to feed it with a 2-bit value.

Altera_Forum · ‎10-09-2012

BEGIN

-- test protokoll case 1

WAIT FOR 100ns;

addr_ram <= "01";

-- test protokoll case 2

WAIT FOR 100ns;

addr_rom <= "10";

-- test protokoll case 3

WAIT FOR 100ns;

data_ram <= "011";

-- test protokoll case 4

WAIT FOR 100ns;

we_ram <= '1';

-- code that executes only once

WAIT;

END PROCESS init;

END uppgift_3b_arch;

i have this

# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(75): (vcom-1272) Length of expected is 3; length of actual is 2.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(97): VHDL Compiler exiting# ** Error: c:/altera/12.0/modelsim_ase/win32aloem/vcom failed.

Altera_Forum · ‎10-10-2012

I already gave you the reason for that error.