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Honored Contributor I
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the clock network delay is different between Timequest report and chip planner

i am learning timequest and sdc, but now i have some confusion with the difference of the clock network delay between Timequest report and chip planner. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=931&stc=1&thumb=1&d=1234492083  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=932&stc=1&thumb=1&d=1234492304  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=933&stc=1&thumb=1&d=1234492310  

in the first pic,the clock network delay is 2.050ns,i think that : 

the clock network delay time = pin delay time + routing delay time 

 

we can get the pin delay time from the third pic, is 1.163ns, and also we can get the routing delay time from the second pic, is 1.600ns. 

now the problem comes, the equal is wrong, or i am wrong with the equal, can anybody give me some suggestion, pls. 

thank you!
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Honored Contributor I
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Do not use the Chip Planner for any sort of static timing analysis. TimeQuest is 100% the way to go. Note that every timing analysis has micro-parameters(uTsu, uTh) on the same registers, so timing changes depending on what type of analysis you're doing. Also note that TQ models On-Chip Variation(OCV), so at the same timing model the same path may have two different results, one for setup analysis and one for hold analysis, where the Chip Planner does not do this(and I'd guess always show the slower). Note that the Chip Planner may not show the entire delay, i.e. if going to an output pad, it may not show the final output buffer.  

Always use TimeQuest for your true numbers. If you need more detail, change report_timing -detail to full_path. If you want even more than that, add "-show_routing" to the command(although this tends to be too much). 

I use Chip Planner all the time with TimeQuest, where TQ gives me the exact numbers, and Chip Planner gives me a nice better visualization of what's going on, but as I've said, the real numebers should be form TQ.
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Honored Contributor I
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you are right Rysc, i try the slow model and fast model, the delay time in chip planner is not change, but the time in TQ changed. 

thanks for your help!
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Honored Contributor I
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Note that even in the slow model, if you do a setup analysis or hold analysis on the exact same path, you will end up with different numbers(for 65nm and newer families). This is correct, but the Chip Planner won't convey that.

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